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1.发明授权Systems and methods for integrated circuits comprising multiple body biasing domains 有权包括多个主体偏置域的集成电路的系统和方法公开(公告)号：US08420472B2
公开(公告)日：2013-04-16
申请号：US12873062
申请日：2010-08-31
IPC分类号： H01L29/72
CPC分类号： H01L21/823892 , H01L21/743 , H01L21/761 , H01L21/823878 , H01L29/78
摘要： Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment of the present invention, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.
摘要翻译： 包括多个主体偏置域的集成电路的系统和方法。 根据本发明的第一实施例，半导体结构包括第一类型材料的衬底。 包括第二类型材料的壁的第一封闭结构从衬底的表面延伸到第一深度。 所述第二类型材料的下面并耦合到所述封闭结构的平面深井从所述第一深度延伸到第二深度。 所述第二类型材料的封闭结构和平面深孔形成第一类型材料的电隔离区域。 第二类型半导体器件设置成从第一类型材料的电隔离区域接收第一主体偏置电压。 形成在第一类型材料的电绝缘区域内的第二类型材料的阱，并且设置第一类型半导体器件以从第二类型材料的阱接收第二主体偏置电压。
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2.发明申请SYSTEMS AND METHODS FOR INTEGRATED CIRCUITS COMPRISING MULTIPLE BODY BIASING DOMAINS 有权包含多个体积偏移域的集成电路的系统和方法公开(公告)号：US20110086478A1
公开(公告)日：2011-04-14
申请号：US12968032
申请日：2010-12-14
IPC分类号： H01L21/8238
CPC分类号： H03K19/0027 , H03K2217/0018
摘要： Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.
摘要翻译： 包括多个主体偏置域的集成电路的系统和方法。 根据第一实施例，半导体结构包括第一类型材料的衬底。 包括第二类型材料的壁的第一封闭结构从衬底的表面延伸到第一深度。 所述第二类型材料的下面并耦合到所述封闭结构的平面深井从所述第一深度延伸到第二深度。 所述第二类型材料的封闭结构和平面深孔形成第一类型材料的电隔离区域。 第二类型半导体器件设置成从第一类型材料的电隔离区域接收第一主体偏置电压。 形成在第一类型材料的电隔离区域内的第二类型材料的阱，并且设置第一类型半导体器件以从第二类型材料的阱接收第二主体偏置电压。
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3.发明申请SYSTEMS AND METHODS FOR INTEGRATED CIRCUITS COMPRISING MULTIPLE BODY BIASING DOMAINS 有权包含多个体积偏移域的集成电路的系统和方法公开(公告)号：US20100321098A1
公开(公告)日：2010-12-23
申请号：US12873062
申请日：2010-08-31
IPC分类号： H03K3/01
CPC分类号： H01L21/823892 , H01L21/743 , H01L21/761 , H01L21/823878 , H01L29/78
摘要： Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment of the present invention, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.
摘要翻译： 包括多个主体偏置域的集成电路的系统和方法。 根据本发明的第一实施例，半导体结构包括第一类型材料的衬底。 包括第二类型材料的壁的第一封闭结构从衬底的表面延伸到第一深度。 所述第二类型材料的下面并耦合到所述封闭结构的平面深井从所述第一深度延伸到第二深度。 所述第二类型材料的封闭结构和平面深孔形成第一类型材料的电隔离区域。 第二类型半导体器件设置成从第一类型材料的电隔离区域接收第一主体偏置电压。 形成在第一类型材料的电隔离区域内的第二类型材料的阱，并且设置第一类型半导体器件以从第二类型材料的阱接收第二主体偏置电压。
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4.发明授权Systems and methods for integrated circuits comprising multiple body biasing domains 有权包括多个主体偏置域的集成电路的系统和方法公开(公告)号：US08697512B2
公开(公告)日：2014-04-15
申请号：US12968032
申请日：2010-12-14
IPC分类号： H01L29/72
CPC分类号： H03K19/0027 , H03K2217/0018
摘要： Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.
摘要翻译： 包括多个主体偏置域的集成电路的系统和方法。 根据第一实施例，半导体结构包括第一类型材料的衬底。 包括第二类型材料的壁的第一封闭结构从衬底的表面延伸到第一深度。 所述第二类型材料的下面并耦合到所述封闭结构的平面深井从所述第一深度延伸到第二深度。 所述第二类型材料的封闭结构和平面深孔形成第一类型材料的电隔离区域。 第二类型半导体器件设置成从第一类型材料的电隔离区域接收第一主体偏置电压。 形成在第一类型材料的电隔离区域内的第二类型材料的阱，并且设置第一类型半导体器件以从第二类型材料的阱接收第二主体偏置电压。
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公开(公告)号：US07816742B1
公开(公告)日：2010-10-19
申请号：US11400368
申请日：2006-04-06
IPC分类号： H01L29/72
CPC分类号： H01L21/823892 , H01L21/743 , H01L21/761 , H01L21/823878 , H01L29/78
摘要： Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment of the present invention, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.
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6.发明授权Systems and methods for integrated circuits comprising multiple body biasing domains 有权包括多个主体偏置域的集成电路的系统和方法公开(公告)号：US07859062B1
公开(公告)日：2010-12-28
申请号：US10956722
申请日：2004-09-30
IPC分类号： H01L29/72
CPC分类号： H03K19/0027 , H03K2217/0018
摘要： Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment of the present invention, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.
摘要翻译： 包括多个主体偏置域的集成电路的系统和方法。 根据本发明的第一实施例，半导体结构包括第一类型材料的衬底。 包括第二类型材料的壁的第一封闭结构从衬底的表面延伸到第一深度。 所述第二类型材料的下面并耦合到所述封闭结构的平面深井从所述第一深度延伸到第二深度。 所述第二类型材料的封闭结构和平面深孔形成第一类型材料的电隔离区域。 第二类型半导体器件设置成从第一类型材料的电隔离区域接收第一主体偏置电压。 形成在第一类型材料的电隔离区域内的第二类型材料的阱，并且设置第一类型半导体器件以从第二类型材料的阱接收第二主体偏置电压。
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公开(公告)号：US07786756B1
公开(公告)日：2010-08-31
申请号：US11241552
申请日：2005-09-30
IPC分类号： H03K17/16 , H03K19/003 , H03K3/00
CPC分类号： G06F1/3203 , G06F1/305 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Systems and methods of suppressing latchup. In accordance with a first embodiment of the present invention a latchup suppression system comprises a voltage comparator for comparing a voltage applied to a body terminal of a semiconductor device to a reference voltage. The voltage comparator is also for controlling a selective coupling mechanism. The selective coupling mechanism is for selectively coupling the body terminal to a respective power supply. The latchup suppressing system is preferably independent of a voltage supply for applying a voltage to the body terminal.
摘要翻译： 抑制闭锁的系统和方法。 根据本发明的第一实施例，闭锁抑制系统包括用于将施加到半导体器件的主体端子的电压与参考电压进行比较的电压比较器。 电压比较器也用于控制选择性耦合机构。 选择性耦合机构用于将主体端子选择性地耦合到相应的电源。 闩锁抑制系统优选地独立于用于向身体终端施加电压的电压源。
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8.发明授权公开(公告)号：US07765412B1
公开(公告)日：2010-07-27
申请号：US11540117
申请日：2006-09-29
CPC分类号： G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Methods and systems for operating a semiconductor device (e.g., a processor) are described. The device is operating at a first operating condition and device temperature. The first operating condition for the device can be dynamically changed to a second operating condition. The second operating condition is selected considering the design operating life of the device.
摘要翻译： 描述了用于操作半导体器件（例如，处理器）的方法和系统。 该设备在第一个操作条件和设备温度下运行。 设备的第一个操作条件可以动态地更改为第二个操作条件。 考虑到设备的设计使用寿命，选择第二个操作条件。
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公开(公告)号：US20100097092A1
公开(公告)日：2010-04-22
申请号：US12651244
申请日：2009-12-31
IPC分类号： G01R31/28
CPC分类号： H03K3/012 , G01R31/2621 , G05B13/021 , G06F1/3203 , G06F1/324 , G06F1/3296 , H03K3/0315 , Y02D10/126 , Y02D10/172
摘要： Systems and methods for closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a predetermined value of a dynamic operating indicator of the integrated circuit. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the integrated circuit's behavior.
摘要翻译： 集成电路闭环反馈控制系统与方法。 在一个实施例中，调整集成电路的多个可控输入以实现集成电路的动态工作指示器的预定值。 基于集成电路行为的动态操作指示灯，通过闭环反馈来控制集成电路的工作状态。
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公开(公告)号：US08253434B2
公开(公告)日：2012-08-28
申请号：US12651244
申请日：2009-12-31
CPC分类号： H03K3/012 , G01R31/2621 , G05B13/021 , G06F1/3203 , G06F1/324 , G06F1/3296 , H03K3/0315 , Y02D10/126 , Y02D10/172
摘要： Systems and methods for closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a predetermined value of a dynamic operating indicator of the integrated circuit. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the integrated circuit's behavior.
摘要翻译： 集成电路闭环反馈控制系统与方法。 在一个实施例中，调整集成电路的多个可控输入以实现集成电路的动态工作指示器的预定值。 基于集成电路行为的动态操作指示灯，通过闭环反馈来控制集成电路的工作状态。
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