公开(公告)号：US5987628A

公开(公告)日：1999-11-16

申请号：US978807

申请日：1997-11-26

申请人： Vincent Von Bokern ,  Zohar Bogin ,  David Freker

发明人： Vincent Von Bokern ,  Zohar Bogin ,  David Freker

IPC分类号： G06F11/10 ,  G06F11/00

CPC分类号： G06F11/1048

摘要： An apparatus and method for correcting corrupted data. Access logic accesses a memory. Error detection logic generates an error signal for each data value output by the memory to indicate whether the data value has a correctable error. Correction logic requests the access logic to write to the memory a corrected version of each data value indicated by the error signal to have a correctable error.

摘要翻译： 一种校正损坏数据的装置和方法。 访问逻辑访问存储器。 错误检测逻辑为存储器输出的每个数据值产生错误信号，以指示数据值是否具有可校正错误。 校正逻辑请求访问逻辑向存储器写入由错误信号指示的每个数据值的校正版本以具有可校正的错误。

公开(公告)号：US5953685A

公开(公告)日：1999-09-14

申请号：US979835

申请日：1997-11-26

申请人： Zohar Bogin ,  Vincent E. VonBokern

发明人： Zohar Bogin ,  Vincent E. VonBokern

IPC分类号： G11C5/00 ,  G11C8/20 ,  G05D23/00

CPC分类号： G11C5/06 ,  G06F1/206 ,  G06F13/161 ,  G11C5/04 ,  G11C5/143 ,  G11C8/20

摘要： A method for controlling core logic temperature. The core logic having a memory controller and memory components coupled to system memory. The method having the step of determining access rate to the system memory through the core logic and controlling the temperature of the core logic by adjusting the access rate.

摘要翻译： 一种控制核心逻辑温度的方法。 核心逻辑具有存储器控制器和耦合到系统存储器的存储器组件。 该方法具有通过核心逻辑确定对系统存储器的访问速率并通过调整访问速率来控制核心逻辑的温度的步骤。

公开(公告)号：US5889968A

公开(公告)日：1999-03-30

申请号：US939801

申请日：1997-09-30

申请人： Joseph A. Bennett ,  Darren Abramson ,  Michael Derr ,  Zohar Bogin

发明人： Joseph A. Bennett ,  Darren Abramson ,  Michael Derr ,  Zohar Bogin

IPC分类号： G06F13/36 ,  G06F13/14

CPC分类号： G06F13/36

摘要： A method and apparatus is disclosed for providing an interlocked broadcast message that solves the problem of a system component taking action in response to a broadcast message issued by a processor before the processor receives communication that the broadcast message has been delivered. A broadcast message transaction request is issued from a processor. The broadcast message transaction request is posted in a transaction request buffer. A reply is communicated to the processor that the broadcast message transaction request has been posted, and the broadcast message is then delivered over the bus. In an alternative embodiment, after the broadcast message transaction request is issued from the processor, the broadcast message transaction request is stored in a transaction request buffer. The broadcast message is only delivered over the bus once it has been determined that the reply to the processor that the broadcast message transaction has completed can be immediately delivered to the processor following the delivery of the broadcast message.

摘要翻译： 公开了一种用于提供互锁广播消息的方法和装置，其解决了在处理器接收到广播消息已被传送的通信之前响应于由处理器发出的广播消息而采取动作的系统组件的问题。 从处理器发出广播消息交易请求。 广播消息事务请求被发布在事务请求缓冲器中。 向处理器传送广播消息交易请求已经被发布的答复，然后通过总线传送广播消息。 在替代实施例中，在从处理器发出广播消息事务请求之后，广播消息事务请求被存储在事务请求缓冲器中。 一旦确定广播消息交易已经完成的对处理器的答复可以在传送广播消息之后立即传送到处理器，广播消息仅在总线上传送。

公开(公告)号：US5835435A

公开(公告)日：1998-11-10

申请号：US982876

申请日：1997-12-02

申请人： Zohar Bogin ,  David E. Freker

发明人： Zohar Bogin ,  David E. Freker

IPC分类号： G11C5/14 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C8/00

CPC分类号： G11C11/4076 ,  G11C5/14 ,  G11C7/22 ,  G11C8/12

摘要： An apparatus and method for dynamically placing portions of a memory in a reduced power consumption state. Requests to access a memory that includes a plurality of rows of memory components are received. One or more of the plurality of rows of memory components are placed in a reduced power consumption state based on the requests while one or more other rows of the plurality of rows are accessed.

摘要翻译： 一种用于在降低的功耗状态下动态地放置存储器的部分的装置和方法。 接收到访问包括多行存储器组件的存储器的请求。 所述多行存储器组件中的一个或多个在所述多个行中的一个或多个其他行被访问的同时，基于所述请求被置于降低的功耗状态。

公开(公告)号：US08291415B2

公开(公告)日：2012-10-16

申请号：US12347988

申请日：2008-12-31

申请人： Zohar Bogin ,  Suryaprasad Kareenahalli ,  Rajeev K. Nalawadi ,  Christopher D. Kral

发明人： Zohar Bogin ,  Suryaprasad Kareenahalli ,  Rajeev K. Nalawadi ,  Christopher D. Kral

IPC分类号： G06F9/455

CPC分类号： G06F9/45533

摘要： Apparatuses, methods, and systems for paging instructions for a virtualization engine to local storage. An apparatus includes a processor, a physical device controller, a virtualization engine, system memory, and local storage. The physical device controller is to be shared by a plurality of virtual machines created by a virtual machine monitor installed on a processor. The virtualization engine is to represent the physical device controller as a plurality of virtual device controllers available to be allocated to the plurality of virtual machines. The local storage is separate from the physical memory to store instructions transferred from the system memory for execution by the virtualization engine.

摘要翻译： 用于虚拟化引擎到本地存储的寻呼指令的设备，方法和系统。 一种装置包括处理器，物理设备控制器，虚拟化引擎，系统存储器和本地存储器。 物理设备控制器将由安装在处理器上的虚拟机监视器创建的多个虚拟机共享。 虚拟化引擎将物理设备控制器表示为可被分配给多个虚拟机的多个虚拟设备控制器。 本地存储与物理内存分离，以存储从系统内存传输的指令，供虚拟化引擎执行。

公开(公告)号：US20100169885A1

公开(公告)日：2010-07-01

申请号：US12347988

申请日：2008-12-31

申请人： Zohar Bogin ,  Suryaprasad Kareenahalli ,  Rajeev K. Nalawadi ,  Christopher D. Kral

发明人： Zohar Bogin ,  Suryaprasad Kareenahalli ,  Rajeev K. Nalawadi ,  Christopher D. Kral

IPC分类号： G06F9/455

CPC分类号： G06F9/45533

摘要： Embodiments of apparatuses, methods, and systems for paging instructions for a virtualization engine to local storage are disclosed. In one embodiment, an apparatus includes a processor, a physical device controller, a virtualization engine, system memory, and local storage. The physical device controller is to be shared by a plurality of virtual machines created by a virtual machine monitor installed on a processor. The virtualization engine is to represent the physical device controller as a plurality of virtual device controllers available to be allocated to the plurality of virtual machines. The local storage is separate from the physical memory to store instructions transferred from the system memory for execution by the virtualization engine.

摘要翻译： 公开了用于虚拟化引擎到本地存储器的寻呼指令的装置，方法和系统的实施例。 在一个实施例中，一种装置包括处理器，物理设备控制器，虚拟化引擎，系统存储器和本地存储器。 物理设备控制器将由安装在处理器上的虚拟机监视器创建的多个虚拟机共享。 虚拟化引擎将物理设备控制器表示为可被分配给多个虚拟机的多个虚拟设备控制器。 本地存储与物理内存分离，以存储从系统内存传输的指令，供虚拟化引擎执行。

公开(公告)号：US20100169884A1

公开(公告)日：2010-07-01

申请号：US12347978

申请日：2008-12-31

申请人： Zohar Bogin ,  Suryaprasad Kareenahalli ,  Rajeev K. Nalawadi ,  Eric Ferrara

发明人： Zohar Bogin ,  Suryaprasad Kareenahalli ,  Rajeev K. Nalawadi ,  Eric Ferrara

IPC分类号： G06F9/455

CPC分类号： G06F9/45533

摘要： Embodiments of apparatuses, methods, and systems for injecting transactions to support the virtualization of a physical device controller are disclosed. In one embodiment, an apparatus includes a processor, system memory, a physical device controller, and a virtualization agent. The physical device controller is to be shared by a plurality of virtual machines created by a virtual machine monitor installed on a processor. The virtualization agent is coupled to the system memory through a first interface and coupled to the physical device controller through a second interface, to represent the physical device controller as a plurality of virtual device controllers available to be allocated to the plurality of virtual machines, and to inject transactions onto the first interface and the second interface on behalf of the plurality of virtual device controllers.

摘要翻译： 公开了用于注入事务以支持物理设备控制器的虚拟化的装置，方法和系统的实施例。 在一个实施例中，一种装置包括处理器，系统存储器，物理设备控制器和虚拟化代理。 物理设备控制器将由安装在处理器上的虚拟机监视器创建的多个虚拟机共享。 虚拟化代理通过第一接口耦合到系统存储器，并通过第二接口耦合到物理设备控制器，以将物理设备控制器表示为可被分配给多个虚拟机的多个虚拟设备控制器;以及 以代表多个虚拟设备控制器将事务注入第一接口和第二接口。

公开(公告)号：US20080250183A1

公开(公告)日：2008-10-09

申请号：US12048556

申请日：2008-03-14

申请人： Zohar Bogin ,  Brent D. Chartrand ,  Arthur D. Hunter ,  Mihir Shah

发明人： Zohar Bogin ,  Brent D. Chartrand ,  Arthur D. Hunter ,  Mihir Shah

IPC分类号： G06F13/14

CPC分类号： G06F3/16 ,  G10L19/0018

摘要： Machine-readable media, methods, and apparatus are described to recover from stream under-run and/or over-run conditions. In some embodiments, an audio controller may discard any partial sample block of the stream.

摘要翻译： 描述了机器可读介质，方法和装置，以从流下运行和/或超载条件中恢复。 在一些实施例中，音频控制器可以丢弃流的任何部分采样块。

公开(公告)号：US20080159022A1

公开(公告)日：2008-07-03

申请号：US11648855

申请日：2006-12-29

申请人： Suryaprasad Kareenahalli ,  Zohar Bogin

发明人： Suryaprasad Kareenahalli ,  Zohar Bogin

IPC分类号： G11C7/22

CPC分类号： G06F13/4054

摘要： An integrated circuit communicates with memory devices. Data from the memory devices arrives at the integrated circuit with varying propagation delays. The integrated circuit detects the arrival of data from the memory devices, and stores the data in FIFOs. A FIFO drain signal is generated responsive to the detection of the data arrival.

摘要翻译： 集成电路与存储器件通信。 来自存储器件的数据到达具有变化的传播延迟的集成电路。 集成电路检测来自存储器件的数据的到达，并将数据存储在FIFO中。 响应于数据到达的检测而产生FIFO漏极信号。

公开(公告)号：US07350030B2

公开(公告)日：2008-03-25

申请号：US11172401

申请日：2005-06-29

申请人： Hemant G. Rotithor ,  Abhishek Singhal ,  Randy B. Osborne ,  Zohar Bogin ,  Raul N. Gutierrez ,  Buderya S. Acharya ,  Surya Kareenahalli

发明人： Hemant G. Rotithor ,  Abhishek Singhal ,  Randy B. Osborne ,  Zohar Bogin ,  Raul N. Gutierrez ,  Buderya S. Acharya ,  Surya Kareenahalli

IPC分类号： G06F12/00 ,  G06F9/00

CPC分类号： G06F12/0862 ,  G06F12/0215 ,  G06F12/0607 ,  G06F2212/6022 ,  G06F2212/6026

摘要： The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a channel mapper to map the prefetches to each channel of the memory device, a scheduler to schedule the prefetches onto the memory device in a DRAM-state aware manner, a throttling heuristic to scale the number of prefetches, and a prefetch data buffer to store prefetch data. The method of prefetching comprises tracking the state of streams, detecting a stride on one of the streams, selecting the stream with the stride for prefetch injection, enqueueing prefetches from the selected stream, mapping the prefetches to each of the interleaved channels, injecting the prefetches from the selected stream into each of the interleaved channels, and scheduling the prefetches onto the memory device in a DRAM-state aware manner.

摘要翻译： 本发明包括一种从具有交织信道的存储装置预取的装置和方法。 芯片组预取器包括用于检测流中的步幅的步幅检测器，用于将预取插入存储器件的预取注入器，用于将预取映射到存储器件的每个通道的通道映射器，调度器以将预取计划到存储器上 DRAM状态感知方式的设备，限制预取数量的限制启发式，以及预取数据缓冲器来存储预取数据。 预取方法包括跟踪流的状态，检测一条流上的步幅，选择用于预取注入的步幅的流，从所选择的流中引入预取，将预取映射到每个交错通道，注入预取 从所选择的流到每个交织的信道，并且以DRAM状态感知的方式将预取调度到存储器设备上。