公开(公告)号：US06486515B2

公开(公告)日：2002-11-26

申请号：US10131536

申请日：2002-04-24

申请人： Song Jun ,  Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek

发明人： Song Jun ,  Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek

IPC分类号： H01L2362

CPC分类号： H01L27/0251 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. An N-well is formed within a silicon semiconductor substrate. A P+ region is implanted within a portion of the N-well and an N+ region is implanted within a portion of the semiconductor substrate not occupied by the N-well. An oxide layer is formed overlying the semiconductor substrate and patterned to form openings to the semiconductor substrate. An epitaxial silicon layer is grown within the openings and overlying the oxide layer. Shallow trench isolation regions are formed within the epitaxial silicon layer extending to the underlying oxide layer. Gate electrodes and associated source and drain regions are formed in and on the epitaxial silicon layer between the shallow trench isolation regions. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. The interlevel dielectric layer is covered with a mask that covers the first contact openings. Second contact openings are opened through the interlevel dielectric layer, shallow trench isolations, and the oxide layer to the N+ region and P+ region. The mask is removed. The first and second contact openings are filled with a conducting layer to complete formation of an ESD device.

摘要翻译： 描述了使用绝缘体上硅技术形成静电放电装置的方法。 在硅半导体衬底内形成N阱。 将P +区注入到N阱的一部分内，并且将N +区注入到不被N阱占据的半导体衬底的一部分内。 在半导体衬底上形成氧化物层并图案化以形成到半导体衬底的开口。 外延硅层生长在开口内并覆盖氧化物层。 在延伸到下面的氧化物层的外延硅层内形成浅沟槽隔离区。 在浅沟槽隔离区域之间的外延硅层中和栅极电极和相关的源极和漏极区域上形成栅电极。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 用覆盖第一接触开口的掩模覆盖层间电介质层。 第二接触开口通过层间介质层，浅沟槽隔离层和氧化物层开放到N +区域和P +区域。 去除面具。 第一和第二接触开口填充有导电层以完成ESD装置的形成。

公开(公告)号：US06284609B1

公开(公告)日：2001-09-04

申请号：US09435437

申请日：1999-11-22

申请人： Ting Cheong Ang ,  Shyue Fong Quek ,  Puay Ing Ong ,  Sang Yee Loong

发明人： Ting Cheong Ang ,  Shyue Fong Quek ,  Puay Ing Ong ,  Sang Yee Loong

IPC分类号： H01L21336

CPC分类号： H01L29/66628 ,  H01L21/2257 ,  H01L21/28026 ,  H01L21/2807 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7834

摘要： A new method of fabricating a sub-quarter micron MOSFET device is achieved. A semiconductor substrate is provided. Isolation regions are formed in this substrate. An oxide layer is provided overlying both the substrate and the isolation regions. The oxide layer is patterned and etched exposing two regions of the substrate. A selective epitaxial growth (SEG) is performed with in situ doping covering the two exposed substrate regions formed during the previous step. The doped SEG regions will form the source and drain contact regions of the MOSFET. The oxide layer region between the two doped SEG regions is then patterned and etched away exposing the substrate. This is followed by a gate oxide formation and either a polysilicon or metal gate deposition. Planarization is then performed on the surface to facilitate interconnection later in the process and to form the final gate structure. Thermal energy provided from processing steps or from a rapid thermal anneal (RTA) allows the doping atoms in the SEG regions to diffuse into the substrate thereby forming the active source/drain regions. This method allows precise control of the doping profile in the active source/drain region. An interlevel dielectric is then deposited over the entire surface. Contact holes are then etched in the interlevel dielectric and metalization patterned to allow interconnection to the completed MOSFET device.

摘要翻译： 实现了制造二分之一微米MOSFET器件的新方法。 提供半导体衬底。 在该衬底中形成隔离区。 提供覆盖衬底和隔离区域的氧化物层。 图案化和蚀刻氧化层暴露衬底的两个区域。 通过原位掺杂来执行选择性外延生长（SEG），覆盖在前一步骤期间形成的两个暴露的衬底区域。 掺杂的SEG区域将形成MOSFET的源极和漏极接触区域。 然后将两个掺杂的SEG区域之间的氧化物层区域图案化并蚀刻掉，暴露衬底。 之后是栅极氧化物形成和多晶硅或金属栅极沉积。 然后在表面上执行平面化，以便在该过程中稍后进行互连并形成最终的栅极结构。 从加工步骤或快速热退火（RTA）提供的热能允许SEG区域中的掺杂原子扩散到衬底中，从而形成有源源极/漏极区域。 该方法允许精确控制有源源极/漏极区域中的掺杂分布。 然后在整个表面上沉积层间电介质。 然后在层间电介质中蚀刻接触孔，并图案化金属化，以允许与完成的MOSFET器件互连。

公开(公告)号：US06261917B1

公开(公告)日：2001-07-17

申请号：US09567420

申请日：2000-05-09

申请人： Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

发明人： Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

IPC分类号： H01L2120

CPC分类号： H01L28/40 ,  H01L21/31683 ,  H01L28/75

摘要： A method for fabricating a metal-oxide-metal capacitor is described. A first insulating layer is provided overlying a semiconductor substrate. A barrier metal layer and a first metal layer are deposited over the insulating layer. A titanium layer is deposited overlying the first metal layer. The titanium layer is exposed to an oxidizing plasma while simultaneously a portion of the titanium layer where the metal-oxide-metal capacitor is to be formed is exposed to light whereby the portion of the titanium layer exposed to light reacts with the oxidizing plasma to form titanium oxide. Thereafter, the titanium layer is removed, leaving the titanium oxide layer where the metal-oxide-metal capacitor is to be formed. A second metal layer is deposited overlying the first metal layer and the titanium oxide layer. The second metal layer, titanium oxide layer, and first metal layer are patterned to form a metal-oxide-metal capacitor wherein the second metal layer forms an upper plate electrode, the titanium oxide layer forms a capacitor dielectric, and the first metal layer forms a bottom plate electrode of the MOM capacitor.

摘要翻译： 对金属氧化物 - 金属电容器的制造方法进行说明。 第一绝缘层设置在半导体衬底上。 在绝缘层上沉积阻挡金属层和第一金属层。 沉积钛层沉积在第一金属层上。 将钛层暴露于氧化等离子体，同时将要形成金属 - 氧化物 - 金属电容器的钛层的一部分暴露于光，由此暴露于光的钛层的部分与氧化等离子体反应形成 氧化钛。 然后，除去钛层，留下要形成金属 - 氧化物 - 金属电容器的氧化钛层。 沉积在第一金属层和氧化钛层上的第二金属层。 对第二金属层，氧化钛层和第一金属层进行构图以形成金属氧化物 - 金属电容器，其中第二金属层形成上板电极，氧化钛层形成电容器电介质，第一金属层形成 MOM电容器的底板电极。

公开(公告)号：US06455384B2

公开(公告)日：2002-09-24

申请号：US09972645

申请日：2001-10-09

申请人： Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

发明人： Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

IPC分类号： H01L21336

CPC分类号： H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

摘要： A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions. Additional iterations include the use of an L shaped spacer, overlying the source/drain extension region, as well as the formation of metal silicide, on the doped SEG silicon regions, and on the gate structures.

摘要翻译： 已经开发了一种用于制造MOSFET器件的方法，其特征在于在利用高温工艺（例如重掺杂源极/漏极区域）之后形成的源极/漏极延伸区域。 在掺杂的SEG硅区域的侧面上形成一次性绝缘体间隔物，随后在位于掺杂的SEG硅区域之间的半导体衬底的区域上形成栅极绝缘体层和覆盖栅极结构。 在这些工艺步骤中经历的温度导致SEG硅区域下方的重掺杂源极/漏极的形成。 选择性地去除一次性间隔件允许源极/漏极延伸区域被放置在与重掺杂的源极/漏极区域相邻的由一次性间隔物空出的空间中。 然后使用绝缘体间隔物来填充通过去除一次性间隔件而空出的空间，直接覆盖源极/漏极延伸区域。 另外的迭代包括在掺杂的SEG硅区域上以及栅极结构上使用覆盖源极/漏极延伸区域的L形间隔物以及金属硅化物的形成。

公开(公告)号：US06329253B1

公开(公告)日：2001-12-11

申请号：US09434922

申请日：1999-11-05

申请人： Jun Song ,  Yonqzang Zhang ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Cai ,  Puay Ing Ong

发明人： Jun Song ,  Yonqzang Zhang ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Cai ,  Puay Ing Ong

IPC分类号： H01L21336

CPC分类号： H01L29/66621 ,  H01L21/76224 ,  H01L27/0266 ,  H01L29/7834

摘要： A method for forming a novel thick oxide electrostatic discharge device using shallow trench isolation technology is described. A trench is etched into a semiconductor substrate. An oxide layer is deposited overlying the semiconductor substrate and filling the trench. The oxide within the trench is partially etched away leaving the oxide on the sidewalls and bottom of the trench. The oxide is polished away to the surface of the semiconductor substrate whereby oxide remains only on the sidewalls and bottom of the trench. A gate is formed within the trench whereby the gate is surrounded by the oxide. First ions are implanted into the semiconductor substrate adjacent to the trench to form N-wells. Second ions are implanted into the semiconductor substrate in a top portion of the N-wells to form source/drain regions. Third ions are implanted into the semiconductor substrate underlying the N-wells and underlying the trench to form electrostatic discharge trigger taps. This completes formation of an electrostatic discharge device in the fabrication of integrated circuits.

摘要翻译： 描述了使用浅沟槽隔离技术形成新的厚氧化物静电放电装置的方法。 将沟槽蚀刻到半导体衬底中。 沉积在半导体衬底上并填充沟槽的氧化物层。 部分地蚀刻沟槽内的氧化物，留下沟槽的侧壁和底部上的氧化物。 氧化物被抛光到半导体衬底的表面，由此氧化物仅保留在沟槽的侧壁和底部上。 在沟槽内形成栅极，由此栅极被氧化物包围。 将第一离子注入到与沟槽相邻的半导体衬底中以形成N阱。 在N阱的顶部将第二离子注入到半导体衬底中以形成源/漏区。 将第三离子注入位于N阱下方并位于沟槽下方的半导体衬底中以形成静电放电触发抽头。 这就形成了集成电路制造中的静电放电装置。

公开(公告)号：US06376319B2

公开(公告)日：2002-04-23

申请号：US09972629

申请日：2001-10-09

申请人： Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

发明人： Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

IPC分类号： H01L21336

CPC分类号： H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

摘要： A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions. Additional iterations include the use of an L shaped spacer, overlying the source/drain extension region, as well as the formation of metal silicide, on the doped SEG silicon regions, and on the gate structures.

摘要翻译： 已经开发了一种用于制造MOSFET器件的方法，其特征在于在利用高温工艺（例如重掺杂源极/漏极区域）之后形成的源极/漏极延伸区域。 在掺杂的SEG硅区域的侧面上形成一次性绝缘体间隔物，随后在位于掺杂的SEG硅区域之间的半导体衬底的区域上形成栅极绝缘体层和覆盖栅极结构。 在这些工艺步骤中经历的温度导致SEG硅区域下方的重掺杂源极/漏极的形成。 选择性地去除一次性间隔件允许源极/漏极延伸区域被放置在与重掺杂的源极/漏极区域相邻的由一次性间隔物空出的空间中。 然后使用绝缘体间隔物来填充通过去除一次性间隔件而空出的空间，直接覆盖源极/漏极延伸区域。 另外的迭代包括在掺杂的SEG硅区域上以及栅极结构上使用覆盖源极/漏极延伸区域的L形间隔物以及金属硅化物的形成。

公开(公告)号：US06275089B1

公开(公告)日：2001-08-14

申请号：US09482048

申请日：2000-01-13

申请人： Jun Song ,  Ting Cheong Ang ,  Shyue Fong Quek ,  Lap Chan

发明人： Jun Song ,  Ting Cheong Ang ,  Shyue Fong Quek ,  Lap Chan

IPC分类号： H03K508

CPC分类号： H01L27/0251

摘要： A transient protection circuit is described which provides electrostatic discharge (ESD) protection for an internal circuit of an IC. The transient protection circuit comprises two Zener diodes connected in series between the input pad and the internal circuit of the IC. A sufficiently large ESD pulse will drive one the two Zener diodes into breakdown mode, thereby reducing the magnitude of the ESD pulse to the remainder of the circuit. Resistive means are paralleled with the Zener diodes to provide a signal path at non-ESD voltages. To help shunt the ESD current away from the internal circuit, PMOS and NMOS transistors are connected in parallel between the positive and the negative voltage supply and their junction is connected to the internal circuit. Negative ESD pulses cause the PMOS transistors to turn on, dumping the ESD energy into the positive voltage supply, while positive ESD pulses cause the NMOS transistors to turn on, dumping the ESD energy into the negative voltage supply. Voltage changes, caused by currents flowing through the resistive means, trigger parasitic SCRs into conduction to provide the bulk of the ESD protection.

摘要翻译： 描述了为IC的内部电路提供静电放电（ESD）保护的瞬态保护电路。 瞬态保护电路包括串联连接在输入焊盘和IC内部电路之间的两个齐纳二极管。 足够大的ESD脉冲将驱动两个齐纳二极管中的一个进入击穿模式，从而将ESD脉冲的幅度减小到电路的其余部分。 电阻性装置与齐纳二极管并联，以在非ESD电压下提供信号路径。 为了有助于将ESD电流从内部电路分流，PMOS和NMOS晶体管并联连接在正电压和负电源之间，它们的结连接到内部电路。 负ESD脉冲导致PMOS晶体管导通，将ESD能量转储到正电压源中，而正的ESD脉冲使NMOS晶体管导通，将ESD能量转储到负电源。 由电流流过电阻的电流引起的电压变化会将寄生的SCR触发导通，以提供大量的ESD保护。

公开(公告)号：US06177324B1

公开(公告)日：2001-01-23

申请号：US09428568

申请日：1999-10-28

申请人： Jun Song ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Lap Chan

发明人： Jun Song ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Lap Chan

IPC分类号： H01L21336

CPC分类号： H01L29/66621 ,  H01L27/0266 ,  H01L29/0649 ,  H01L29/7834

摘要： A new method is provided for the creation of an ESD protection device for deep submicron semiconductor technology. An STI trench is created and filled with oxide. The surface of the STI region is polished after which a gate structure is created over the STI region. A high energy ESD implant is performed that is self-aligned with the created gate structure after which the EDS device structure is completed by implanting the source and drain regions of the ESD device.

摘要翻译： 提供了一种用于创建深亚微米半导体技术的ESD保护器件的新方法。 产生STI沟槽并填充氧化物。 抛光STI区域的表面，之后在STI区域上形成栅极结构。 执行高能量ESD注入，其与所产生的栅极结构自对准，之后通过注入ESD器件的源极和漏极区域来完成EDS器件结构。

公开(公告)号：US06492242B1

公开(公告)日：2002-12-10

申请号：US09609447

申请日：2000-07-03

申请人： Alex See ,  Cher Liang Randall Cha ,  Shyuz Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

发明人： Alex See ,  Cher Liang Randall Cha ,  Shyuz Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

IPC分类号： H01L2120

CPC分类号： H01L28/40 ,  H01L21/31683

摘要： A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures. A second iteration features the exposure of specific regions of an underlying metal layer, to a UV, or to an I line exposure procedure, performed in an oxidizing ambient, with the regions of an underlying metal layer exposed to the UV or I line procedure, via clear regions in an overlying photolithographic plate. This procedure also results in the formation of a high K layer, on a top portion of the underlying metal layer.

摘要翻译： 在高于周围结构所经历的温度的温度下进行的金属氧化物 - 金属电容器结构的高介电常数（高K）层，其特征在于底层金属层的局部氧化， 已经开发 该方法的第一次迭代的特征在于在氧化环境中使用对底层金属层的局部区域进行的激光烧蚀程序。 激光烧蚀过程仅在激光点产生所需的高温，允许在该温度下产生高K层，而不直接暴露于激光烧蚀过程的半导体衬底上的周围结构保持在较低温度 。 第二次迭代的特征在于在氧化环境中进行的底层金属层的特定区域到UV或I线曝光程序，暴露于UV或I线程序的下面的金属层的区域， 通过覆盖光刻板中的透明区域。 该过程还导致在下面的金属层的顶部上形成高K层。

公开(公告)号：US06090691A

公开(公告)日：2000-07-18

申请号：US439366

申请日：1999-11-15

申请人： Ting Cheong Ang ,  Shyue Fong Quek ,  Xing Yu ,  Ying Keung Leung

发明人： Ting Cheong Ang ,  Shyue Fong Quek ,  Xing Yu ,  Ying Keung Leung

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/417 ,  H01L21/22

CPC分类号： H01L29/66492 ,  H01L21/823814 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545 ,  H01L21/2255 ,  H01L29/665

摘要： A method for forming a raised source and drain structure without using selective epitaxial silicon growth. A semiconductor substrate is provided having one or more gate areas covered by dielectric structures. Doped polysilicon structures are adjacent to the dielectric structures on each side and are co-planar with the dielectric structures from a CMP process. The first dielectric structures are removed to form gate openings and a liner oxide layer is formed on the bottom and sidewalls of the gate openings. Dielectric spacers are formed on the liner oxide layer over the sidewalls of the gate openings, and the liner oxide layer is removed from the bottom of the gate openings and from over the doped polysilicon structures. Source and drain regions are formed in the semiconductor substrate by diffusing impurity ions from the doped polysilicon layer. A gate oxide layer and a gate polysilicon layer are formed over the semiconductor structure and the gate polysilicon layer is planarized to form a gate electrode. In a key step, the dielectric spacers are removed to form spacer openings, and impurity ions are implanted through the spacer openings and annealed to form source and drain extensions. The dielectric spacers are reformed and a self-aligned silicide layer is formed on the doped polysilicon structure and the gate electrode. Alternatively, the self-aligned silicide layer can be formed prior to removing the dielectric spacers and implanting ions to form source and drain extensions.

摘要翻译： 一种用于在不使用选择性外延硅生长的情况下形成隆起的源极和漏极结构的方法。 提供具有被介电结构覆盖的一个或多个栅极区域的半导体衬底。 掺杂的多晶硅结构与每一侧上的电介质结构相邻，并且与来自CMP工艺的电介质结构共面。 去除第一电介质结构以形成栅极开口，并且在栅极开口的底部和侧壁上形成衬里氧化物层。 在栅极开口的侧壁上的衬垫氧化物层上形成介质间隔物，并且从栅极开口的底部和掺杂的多晶硅结构上方移除衬里氧化物层。 通过从掺杂多晶硅层扩散杂质离子，在半导体衬底中形成源区和漏区。 在半导体结构上形成栅极氧化物层和栅极多晶硅层，并且平坦化栅极多晶硅层以形成栅电极。 在关键步骤中，去除电介质间隔物以形成间隔开口，并通过间隔开孔注入杂质离子并退火以形成源极和漏极延伸部分。 电介质间隔物被重整，并且在掺杂多晶硅结构和栅电极上形成自对准的硅化物层。 或者，可以在去除电介质间隔物和注入离子以形成源极和漏极延伸部之前形成自对准硅化物层。