公开(公告)号：US20060043417A1

公开(公告)日：2006-03-02

申请号：US11047609

申请日：2005-02-02

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L31/109

CPC分类号： H01L29/8611 ,  H01L29/063 ,  H01L29/868

摘要： A semiconductor layer of n− type is formed on a semiconductor substrate of p− type. A first buried impurity region of n+ type is formed at an interface between the semiconductor substrate and the semiconductor layer. A second buried impurity region of p+ type is formed at an interface between the first buried impurity region and the semiconductor layer. Above the first and second buried impurity regions, a first impurity region of n type is formed in an upper surface of the semiconductor layer. Above the first and second buried impurity regions, a second impurity region of p type is also formed apart from the first impurity region in the upper surface of the semiconductor layer. When the second impurity region becomes higher in potential than the first impurity region, the second impurity region and the second buried impurity region are electrically isolated from each other by a depletion layer.

摘要翻译： 在p型 - 半导体衬底上形成n +型超导体层。 在半导体衬底和半导体层之间的界面处形成n + +型的第一掩埋杂质区。 在第一掩埋杂质区和半导体层之间的界面处形成第二埋层杂质区p + 在第一和第二掩埋杂质区之上，在半导体层的上表面形成n型的第一杂质区。 在第一和第二掩埋杂质区之上，p型的第二杂质区也与半导体层上表面的第一杂质区分开。 当第二杂质区域的电位高于第一杂质区域时，第二杂质区域和第二掩埋杂质区域通过耗尽层彼此电隔离。

公开(公告)号：US06894348B2

公开(公告)日：2005-05-17

申请号：US09834954

申请日：2001-04-16

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/74 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7816 ,  H01L21/74 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/1008 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/7809

摘要： An N+ buried diffusion region is formed between a P− silicon substrate and an N− epitaxial layer and a P+ buried diffusion region is formed between the N+ buried diffusion region and the N− epitaxial layer. An N diffusion region, a P diffusion region and an N diffusion region are formed in the surface for the N− epitaxial layer. The surface of the P+ buried diffusion region located, approximately, beneath the N diffusion region is recessed so as to go far away from the N diffusion region and a narrowed part is formed in this part. Thereby, in the OFF condition, the depletion layer further extends in the part where the narrowed part is formed. As a result, the withstanding voltage of the semiconductor device is increased.

摘要翻译： 在P-硅衬底和N外延层之间形成N +掩埋扩散区，并且在N +掩埋扩散区和N外延层之间形成P +掩埋扩散区。 在N外延层的表面形成N扩散区，P扩散区和N扩散区。 位于N扩散区域附近的P +掩埋扩散区域的表面凹陷，以便远离N扩散区域，并且在该部分中形成变窄的部分。 因此，在OFF状态下，耗尽层在形成有窄部的部分进一步延伸。 结果，半导体器件的耐受电压增加。

公开(公告)号：US06838745B1

公开(公告)日：2005-01-04

申请号：US09041105

申请日：1998-03-12

申请人： Tomohide Terashima ,  Kazuhiro Shimizu

发明人： Tomohide Terashima ,  Kazuhiro Shimizu

IPC分类号： H01L21/761 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L23/58

CPC分类号： H01L29/7322 ,  H01L21/761

摘要： An n-type well is formed in a p−-type semiconductor substrate and a p−-type epitaxial layer is formed on; the n-type well. An n−-type well is formed in the, p-type epitaxial layer on the n-type well so as to allow a RESURF operation. A p-type island is formed in the n−-type well at a position above the n-type well to form an island region for high withstand-voltage separation. Thus, the withstand voltage of the separated island is improved.

摘要翻译： 在p型半导体衬底中形成n型阱，在其上形成p +型外延层; n型井。 在n型阱上的p型外延层中形成n型阱，以使RESURF工作。 在n型阱上方的n型阱中形成p型岛以形成用于高耐压分离的岛区。 因此，提高了分离岛的耐受电压。

公开(公告)号：US06586799B1

公开(公告)日：2003-07-01

申请号：US09325047

申请日：1999-06-03

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L2976

CPC分类号： H01L29/7802 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/66712 ,  H01L29/7395

摘要： A semiconductor device includes a semiconductor layer having a main surface (100a), a first region (101) of a first conductivity type, a second region (102) of a second conductivity type, and a third region (103) of the second conductivity type, the first region (101) and the second region (102) having a first boundary (101a) formed therebetween, the first boundary (101a) being perpendicular to the main surface (100a), the third region (103) being formed in the first region (101) in spaced apart relation to the second region (102), the third region (103) having a depth less than the depth of the first boundary (101a) from the main surface (100a); and a control electrode (201) insulated from and overlying the main surface (100a) and extending from the first boundary (101a) to a second boundary (101b) formed between the first region (101) and the third region (103). The semiconductor device improves a tradeoff between breakdown voltage and on-resistance. A method of manufacturing the semiconductor device is also provided.

摘要翻译： 半导体器件包括具有主表面（100a），第一导电类型的第一区域（101）和第二导电类型的第二区域（102）和第二导电类型的第三区域（103）的半导体层 所述第一区域（101）和所述第二区域（102）具有形成在其间的第一边界（101a），所述第一边界（101a）垂直于所述主表面（100a），所述第三区域（103）形成为 所述第一区域（101）与所述第二区域（102）间隔开，所述第三区域（103）的深度小于所述第一边界（101a）从所述主表面（100a）的深度; 和从第一边界（101a）延伸到形成在第一区域（101）和第三区域（103）之间的第二边界（101b）延伸的控制电极（201）。 半导体器件改善了击穿电压和导通电阻之间的折衷。 还提供了制造半导体器件的方法。

公开(公告)号：US06586780B1

公开(公告)日：2003-07-01

申请号：US08931688

申请日：1997-09-16

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L2974

CPC分类号： H01L27/0623 ,  H01L2924/0002 ,  H03K17/567 ,  H01L2924/00

摘要： A semiconductor device includes a p type semiconductor substrate, a first n type region formed at the semiconductor substrate, a first n channel DMOS transistor formed in the first n type region, a second n type region formed at the semiconductor substrate, a vertical type pnp bipolar transistor formed in the second n type region, and a second n channel DMOS transistor formed in the second n type region. The first n channel DMOS transistor has a drain for receiving a high power supply voltage (Vdc) and a source for supplying an output voltage (Vout). The bipolar transistor has a base connected to the gate of the first n channel DMOS transistor, an emitter connected to the source of the first n channel DMOS transistor, and a collector connected to the ground. The second n channel DMOS transistor has a drain connected to the gate of the first n channel DMOS transistor and a source connected to the ground.

摘要翻译： 半导体器件包括ap型半导体衬底，形成在半导体衬底上的第一n型区域，形成在第一n型区域中的第一n沟道DMOS晶体管，形成在半导体衬底处的第二n型区域，垂直型pnp双极型 形成在第二n型区域中的晶体管，以及形成在第二n型区域中的第二n沟道DMOS晶体管。 第一n沟道DMOS晶体管具有用于接收高电源电压（Vdc）的漏极和用于提供输出电压（Vout）的源极。 双极晶体管具有连接到第一n沟道DMOS晶体管的栅极的基极，连接到第一n沟道DMOS晶体管的源极的发射极和连接到地的集电极。 第二n沟道DMOS晶体管具有连接到第一n沟道DMOS晶体管的栅极的漏极和连接到地的源极。

公开(公告)号：US06573582B2

公开(公告)日：2003-06-03

申请号：US09986906

申请日：2001-11-13

申请人： Yasunori Yamashita ,  Fumitoshi Yamamoto ,  Tomohide Terashima

发明人： Yasunori Yamashita ,  Fumitoshi Yamamoto ,  Tomohide Terashima

IPC分类号： H01L27095

CPC分类号： H01L21/761 ,  H01L27/0766

摘要： A bipolar transistor is formed on a semiconductor substrate. A Schottky diode is formed in the collector region of the bipolar transistor. The collector region and the semiconductor substrate are isolated in potential from each other by potential isolating layers.

公开(公告)号：US06472710B2

公开(公告)日：2002-10-29

申请号：US09881805

申请日：2001-06-18

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L31113

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42364

摘要： A field MOS transistor having a high withstand voltage is disclosed. An island region of an epitaxial layer is surrounded by a heavily-doped isolation layer and a lightly-doped isolation layer formed thereon. A channel region is formed in the island region so as to assume the same doping level as that of the lightly-doped isolation layer. A region is formed below the island region so as to assume the same doping level as that of the heavily-doped isolation layer, thus supplying a back gate voltage to the transistor. The channel formation region is formed simultaneously with formation of the lightly-doped isolation layer, and the region below the island region is formed simultaneously with the heavily-doped isolation layer. As a result, manufacturing processes can be simplified.

公开(公告)号：US06376891B1

公开(公告)日：2002-04-23

申请号：US08684558

申请日：1996-07-19

申请人： Tatsuhiko Nagatani ,  Tomohide Terashima

发明人： Tatsuhiko Nagatani ,  Tomohide Terashima

IPC分类号： H01L2358

CPC分类号： H01L21/761 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/0922

摘要： In a high breakdown voltage semiconductor device, a buried diffusion region is formed on a semiconductor substrate and an epitaxial layer is formed on the buried diffusion region and the substrate. The epitaxial layer includes a low breakdown voltage element region adjoined by a high breakdown voltage isolation region. A method for forming the high breakdown voltage isolation region complies with a Resurf condition by adjusting a thickness and an impurity concentration of the epitaxial layer. Thus, a high breakdown voltage semiconductor device and a manufacturing process therefor is provided, which includes a low breakdown voltage element region and a high breakdown voltage element region, and a high breakdown isolation region separates a high breakdown voltage region without impairing the characteristics of an element formed on the low breakdown voltage element region.

公开(公告)号：US06344678B1

公开(公告)日：2002-02-05

申请号：US09520000

申请日：2000-03-06

申请人： Fumitoshi Yamamoto ,  Tomohide Terashima

发明人： Fumitoshi Yamamoto ,  Tomohide Terashima

IPC分类号： H01L27082

CPC分类号： H01L29/0804 ,  H01L29/7322

摘要： An n− epitaxial layer serving as a collector region is formed on a p-type silicon substrate. A p diffusion layer serving as a base region is formed on the n− epitaxial layer. An n− diffusion layer and an n+ diffusion layer defining an emitter region are formed on the p diffusion layer. A p+ diffusion layer serving as a base contact region for attaining contact with the p diffusion layer is formed with a prescribed interval between the same and the emitter region. Thus obtained is a semiconductor device comprising a transistor suppressing dispersion of a current amplification factor.

摘要翻译： 在p型硅衬底上形成用作集电极区的n外延层。 在n外延层上形成用作基极区的p扩散层。 在p扩散层上形成限定发射极区的n-扩散层和n +扩散层。 用作与p扩散层接触的基极接触区域的p +扩散层在其与发射极区域之间以规定的间隔形成。 这样获得的是包括抑制电流放大因子的色散的晶体管的半导体器件。

公开(公告)号：US06191466B1

公开(公告)日：2001-02-20

申请号：US09395939

申请日：1999-09-14

申请人： Yasunori Yamashita ,  Tomohide Terashima ,  Fumitoshi Yamamoto

发明人： Yasunori Yamashita ,  Tomohide Terashima ,  Fumitoshi Yamamoto

IPC分类号： H01L21336

CPC分类号： H01L27/0611 ,  H01L21/761 ,  H01L29/8611

摘要： A semiconductor device which has few peripheral element malfunctions and superior performance is obtained. The semiconductor device includes a p-type buried layer on a main surface of a semiconductor substrate, an n-type cathode region provided on the p-type buried layer, and a p-type anode region in contact with the side surface of the n-type cathode region, the p-type buried layer being higher than the p-type anode region in acceptor content, and the p-type buried layer being in contact with the bottom surfaces of the anode and cathode regions.

摘要翻译： 获得了具有极少的外围元件故障和优异性能的半导体器件。 半导体器件包括在半导体衬底的主表面上的p型掩埋层，设置在p型掩埋层上的n型阴极区域和与n型阴极区域接触的p型阳极区域 型阴极区，p型埋层比受体含量高于p型阳极区，p型掩埋层与阳极和阴极区的底表面接触。