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公开(公告)号：US06573582B2
公开(公告)日：2003-06-03
申请号：US09986906
申请日：2001-11-13
IPC分类号： H01L27095
CPC分类号： H01L21/761 , H01L27/0766
摘要： A bipolar transistor is formed on a semiconductor substrate. A Schottky diode is formed in the collector region of the bipolar transistor. The collector region and the semiconductor substrate are isolated in potential from each other by potential isolating layers.
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公开(公告)号：US06191466B1
公开(公告)日：2001-02-20
申请号：US09395939
申请日：1999-09-14
IPC分类号： H01L21336
CPC分类号： H01L27/0611 , H01L21/761 , H01L29/8611
摘要： A semiconductor device which has few peripheral element malfunctions and superior performance is obtained. The semiconductor device includes a p-type buried layer on a main surface of a semiconductor substrate, an n-type cathode region provided on the p-type buried layer, and a p-type anode region in contact with the side surface of the n-type cathode region, the p-type buried layer being higher than the p-type anode region in acceptor content, and the p-type buried layer being in contact with the bottom surfaces of the anode and cathode regions.
摘要翻译： 获得了具有极少的外围元件故障和优异性能的半导体器件。 半导体器件包括在半导体衬底的主表面上的p型掩埋层，设置在p型掩埋层上的n型阴极区域和与n型阴极区域接触的p型阳极区域 型阴极区，p型埋层比受体含量高于p型阳极区，p型掩埋层与阳极和阴极区的底表面接触。
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公开(公告)号：US06518158B1
公开(公告)日：2003-02-11
申请号：US09699463
申请日：2000-10-31
IPC分类号： H01L2128
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： The method for manufacturing a semiconductor device includes the steps of: removing an oxide film in a region including a fuse region at the formation of an opening for the formation of a vertical interconnection in an oxide film serving as an upper insulating layer; and forming the vertical interconnection for electrically connecting interconnection layers below and above the oxide film and the interconnection layer placed on an upper side of the oxide film as one upper conductive layer at the same time.
摘要翻译： 半导体器件的制造方法包括以下步骤：在形成用于形成用作上绝缘层的氧化膜中的垂直互连的开口的开口的区域中去除包含熔丝区域的区域中的氧化膜; 并且形成用于将氧化膜的下方和上方的互连层和布置在氧化物膜的上侧上的互连层电连接作为一个上导电层的垂直互连。
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公开(公告)号：US6153915A
公开(公告)日：2000-11-28
申请号：US70915
申请日：1998-05-04
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/088 , H01L27/092 , H01L29/10 , H01L29/41 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/1087 , H01L21/8249 , H01L27/0623 , H01L27/0921
摘要： In a semiconductor device and a method of manufacturing the same according to the invention, a p-type diffusion region for electrically connecting a back gate region and an electrode layer together is formed at a source region. Thereby, both of source region and p-type diffusion region are electrically connected to the electrode layer, so that the source region and the back gate region are maintained at the same potential. As a result, it is possible to provide the semiconductor device and the method of manufacturing the same which can suppress operation of a parasitic bipolar transistor formed in the semiconductor device even if a gate electrode has a large width.
摘要翻译： 在根据本发明的半导体器件及其制造方法中，在源极区域形成用于将背栅极区域和电极层电连接的p型扩散区域。 由此，源极区域和p型扩散区域都与电极层电连接，使得源极区域和背面栅极区域保持相同的电位。 结果，即使栅电极具有大的宽度，也可以提供能够抑制形成在半导体器件中的寄生双极晶体管的工作的半导体器件及其制造方法。
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公开(公告)号：US06359318B1
公开(公告)日：2002-03-19
申请号：US09258401
申请日：1999-02-26
IPC分类号： H01L2976
CPC分类号： H01L29/7816 , H01L21/26586 , H01L21/8249 , H01L27/0623 , H01L29/0878 , H01L29/42368 , H01L29/4933 , H01L29/66674 , H01L29/66712 , H01L29/7801 , H01L29/7809
摘要： A gate electrode layer is formed opposite to a p type backgate region posed between an n type source region and an n type epitaxial region, with a gate insulating layer interposed therebetween. A sidewall insulating layer is formed to cover a sidewall of the gate electrode layer. A p type backgate region has a relatively shallow p type diffusion region and a relatively deep p type diffusion region. The relatively deep p type diffusion region has a portion overlapping the relatively shallow p type diffusion region, and has its end portion at the substrate surface located directly beneath the sidewall insulating layer. Accordingly, a semiconductor device and a manufacturing method thereof that allow easy control of the threshold voltage of a DMOS transistor and facilitate realization of a rapidly operating bipolar transistor are attained.
摘要翻译： 与n型源极区域和n型外延区域之间的p型背栅极区域相对地形成栅极电极层，其间插入有栅极绝缘层。 形成侧壁绝缘层以覆盖栅电极层的侧壁。 p型背栅区具有较浅的p型扩散区和较深的p型扩散区。 相对较深的p型扩散区域具有与较浅的p型扩散区域重叠的部分，并且其端部位于位于侧壁绝缘层正下方的基板表面。 因此，可以实现容易控制DMOS晶体管的阈值电压并促进实现快速操作的双极晶体管的半导体器件及其制造方法。
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公开(公告)号：US06297532B1
公开(公告)日：2001-10-02
申请号：US08787332
申请日：1997-01-27
IPC分类号： H01L2978
CPC分类号： H01L29/408 , H01L21/76801 , H01L21/76804 , H01L23/485 , H01L23/5329 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The present invention aims to provide a semiconductor device in which a satisfactory breakdown voltage can be obtained without increasing its chip size, and a method of manufacturing the same. A first electrode layer and a second electrode layer are formed. An inorganic type silicon oxide film is formed so as to cover first and second electrodes. An organic type silicon oxide film is formed on a surface of inorganic type silicon oxide film above a portion of a surface of first electrode layer. At a region of inorganic type silicon oxide film where organic type silicon oxide film is not formed, a through hole is formed, exposing a portion of a surface of second electrode layer. An interconnection layer is formed so as to be in contact with second electrode layer via through hole and opposing first electrode layer with inorganic and organic type silicon oxide films therebetween.
摘要翻译： 本发明的目的在于提供一种在不增加芯片尺寸的情况下可获得令人满意的击穿电压的半导体器件及其制造方法。 形成第一电极层和第二电极层。 形成无机型氧化硅膜，以覆盖第一和第二电极。 在第一电极层的表面的一部分上方的无机型氧化硅膜的表面上形成有机型氧化硅膜。 在没有形成有机氧化硅膜的无机型氧化硅膜的区域，形成通孔，露出第二电极层的一部分表面。 形成互连层，以便经由通孔与第二电极层接触，并且在其间具有无机和有机型氧化硅膜的相对的第一电极层。
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7.发明授权Semiconductor device having a Bi-CMOS transistor including an n-channel MOS transistor 失效具有包括n沟道MOS晶体管的Bi-CMOS晶体管的半导体器件
公开(公告)号：US5763926A
公开(公告)日：1998-06-09
申请号：US742120
申请日：1996-10-31
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/088 , H01L27/092 , H01L29/10 , H01L29/41 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/1087 , H01L21/8249 , H01L27/0623 , H01L27/0921
摘要： In a semiconductor device and a method of manufacturing the same according to the invention, a p-type diffusion region for electrically connecting a back gate region and an electrode layer together is formed at a source region. Thereby, both of source region and p-type diffusion region are electrically connected to the electrode layer, so that the source region and the back gate region are maintained at the same potential. As a result, it is possible to provide the semiconductor device and the method of manufacturing the same which can suppress operation of a parasitic bipolar transistor formed in the semiconductor device even if a gate electrode has a large width.
摘要翻译： 在根据本发明的半导体器件及其制造方法中，在源极区域形成用于将背栅极区域和电极层电连接的p型扩散区域。 由此，源极区域和p型扩散区域都与电极层电连接，使得源极区域和背面栅极区域保持相同的电位。 结果，即使栅电极具有大的宽度，也可以提供能够抑制形成在半导体器件中的寄生双极晶体管的工作的半导体器件及其制造方法。
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公开(公告)号：US06344678B1
公开(公告)日：2002-02-05
申请号：US09520000
申请日：2000-03-06
IPC分类号： H01L27082
CPC分类号： H01L29/0804 , H01L29/7322
摘要： An n− epitaxial layer serving as a collector region is formed on a p-type silicon substrate. A p diffusion layer serving as a base region is formed on the n− epitaxial layer. An n− diffusion layer and an n+ diffusion layer defining an emitter region are formed on the p diffusion layer. A p+ diffusion layer serving as a base contact region for attaining contact with the p diffusion layer is formed with a prescribed interval between the same and the emitter region. Thus obtained is a semiconductor device comprising a transistor suppressing dispersion of a current amplification factor.
摘要翻译： 在p型硅衬底上形成用作集电极区的n外延层。 在n外延层上形成用作基极区的p扩散层。 在p扩散层上形成限定发射极区的n-扩散层和n +扩散层。 用作与p扩散层接触的基极接触区域的p +扩散层在其与发射极区域之间以规定的间隔形成。 这样获得的是包括抑制电流放大因子的色散的晶体管的半导体器件。
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9.发明授权Semiconductor device having a device formation region protected from a counterelectromotive force 失效具有防止反电动势的装置形成区域的半导体装置公开(公告)号：US06639294B2
公开(公告)日：2003-10-28
申请号：US10191472
申请日：2002-07-10
IPC分类号： H01L2941
CPC分类号： H01L21/761 , H01L27/0623
摘要： A semiconductor device includes an epitaxial layer formed on a P type silicon substrate; a P+ diffusion layer for dividing the epitaxial layer into an N− epi layer, which constitutes a device formation region, and an N− epi layer, which constitutes an invalid area; and an aluminum wire for electrically connecting the N− epi layer (invalid area) to the P+ diffusion layer. Since the potential of the N− epi layer (invalid area) can be made equal to that of the P+ diffusion layer, it is possible to prevent the electron supply from the P+ diffusion layer to the invalid area even when electrons are supplied to the device formation region by a counterelectromotive force produced by a load having an inductance L.
摘要翻译： 半导体器件包括在P型硅衬底上形成的外延层; 用于将外延层划分成构成器件形成区域的N外延层的P +扩散层和构成无效区域的N外延层; 以及用于将N外延层（无效区域）电连接到P +扩散层的铝线。 由于N外延层（无效区域）的电位可以等于P +扩散层的电位，所以即使向电子提供电子，也可以防止从P +扩散层向无效区域的电子供给 通过由具有电感L的负载产生的反电动势形成区域。
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10.发明申请Semiconductor device, driver circuit and manufacturing method of semiconductor device 有权半导体器件，驱动电路及半导体器件的制造方法公开(公告)号：US20060180862A1
公开(公告)日：2006-08-17
申请号：US11352344
申请日：2006-02-13
CPC分类号： H01L29/78606 , H01L21/84 , H01L27/12 , H01L29/0847 , H01L29/1083 , H01L29/66659 , H01L29/7835 , H01L29/78624
摘要： The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS transistor are formed in an n− type semiconductor layer in an SOI substrate. In addition, an n type impurity region is formed in the semiconductor layer. The impurity region is formed over the entire bottom of the source region at a portion directly below this source region, and is also formed directly below the semiconductor layer between the source region and the drain region. A peak position of an impurity concentration in the impurity region is set below a lowest end of the source region at a portion directly below an upper surface of the semiconductor layer between the source region and the drain region.
摘要翻译： 本发明提供一种半导体技术，能够抑制晶体管的阈值电压的增加，并且还提高源极区域和漏极区域之间的耐受电压。 在SOI衬底中的n + O型半导体层中形成p沟道型MOS晶体管的源极和漏极区域。 此外，在半导体层中形成n型杂质区。 杂质区域形成在源极区域的正下方的源极区域的整个底部上，并且也形成在源极区域和漏极区域之间的半导体层的正下方。 将杂质区域中的杂质浓度的峰值位置设定在源极区域和源极区域之间的半导体层的正上方的正下方的源极区域的最下端。
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