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89 条记录 (耗时 0.021 秒)

    Snubber circuit
    21.
    发明授权
    Snubber circuit 有权
    缓冲电路

    公开(公告)号：US07319579B2

    公开(公告)日：2008-01-15

    申请号：US11185744

    申请日：2005-07-21

    申请人： Tomoki Inoue ,  Koichi Sugiyama

    发明人： Tomoki Inoue ,  Koichi Sugiyama

    IPC分类号： H02H9/06 ,  H02H7/12

    CPC分类号： H02H9/041

    摘要： A snubber circuit has a voltage detection circuit which detects that a voltage between first and second terminals exceeds a predetermined voltage, a protection circuit which performs control to prevent an overvoltage between the first and second terminals when the voltage detection circuit detects that the voltage between the first and second terminals exceeds the predetermined voltage, and a voltage control circuit which bypasses a portion of a main current flowing between the first and second terminals to the protection circuit when the voltage detection circuit detects that the voltage between the first and second terminals exceeds the predetermined voltage.

    摘要翻译： 缓冲电路具有检测第一和第二端子之间的电压超过预定电压的电压检测电路，当电压检测电路检测到第二和第二端子之间的电压时，执行控制以防止第一和第二端子之间的过电压的保护电路 第一和第二端子超过预定电压，以及电压控制电路，当电压检测电路检测到第一和第二端子之间的电压超过第一端子和第二端子之间的电压时，旁路第一和第二端子之间流过的主电流的一部分到保护电路 预定电压。

    Semiconductor device
    22.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20050161768A1

    公开(公告)日：2005-07-28

    申请号：US11016810

    申请日：2004-12-21

    申请人： Koichi Sugiyama ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Masakazu Yamaguchi

    发明人： Koichi Sugiyama ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Masakazu Yamaguchi

    IPC分类号： H01L29/78 ,  H01L27/04 ,  H01L27/088 ,  H01L29/423 ,  H01L29/739 ,  H01L31/113

    CPC分类号： H01L29/7397 ,  H01L29/4232 ,  H01L29/42372 ,  H01L29/7395

    摘要： A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by embedding an electrically conductive material into a plurality of trenches via gate insulating films, the plurality of trenches being formed such that bottoms of the trenches reach the first base layer; source layers of the first conductive type which are formed on a surface area of the second base layer so as to be adjacent to both side walls of the trench provided with the first gate electrode and one side wall of the trench provided with the second gate electrode, respectively; an emitter layer of the second conductive type which is formed on the second surface; emitter electrodes which are formed on the second base layer and the source layers; a collector electrode which is formed on the emitter layer; and first and second terminals which are electrically connected to the first and second gate electrodes, respectively.

    摘要翻译： 半导体器件包括具有第一表面和第二表面的第一导电类型的第一基底层; 形成在第一表面上的第二导电类型的第二基层; 通过经由栅极绝缘膜将导电材料嵌入多个沟槽而形成的第一和第二栅电极，所述多个沟槽形成为使得沟槽的底部到达第一基底层; 源极层，其形成在第二基极层的表面区域上，以与设置有第一栅电极的沟槽的两个侧壁相邻，并且设置有第二栅电极的沟槽的一个侧壁 ， 分别; 形成在第二表面上的第二导电类型的发射极层; 在第二基极层和源极层上形成的发射极; 在发射极层上形成的集电极; 以及分别电连接到第一和第二栅电极的第一和第二端子。

    Semiconductor device
    24.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US07075168B2

    公开(公告)日：2006-07-11

    申请号：US11016810

    申请日：2004-12-21

    申请人： Koichi Sugiyama ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Masakazu Yamaguchi

    发明人： Koichi Sugiyama ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Masakazu Yamaguchi

    IPC分类号： H01L27/102

    CPC分类号： H01L29/7397 ,  H01L29/4232 ,  H01L29/42372 ,  H01L29/7395

    摘要： A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by embedding an electrically conductive material into a plurality of trenches via gate insulating films, the plurality of trenches being formed such that bottoms of the trenches reach the first base layer; source layers of the first conductive type which are formed on a surface area of the second base layer so as to be adjacent to both side walls of the trench provided with the first gate electrode and one side wall of the trench provided with the second gate electrode, respectively; an emitter layer of the second conductive type which is formed on the second surface; emitter electrodes which are formed on the second base layer and the source layers; a collector electrode which is formed on the emitter layer; and first and second terminals which are electrically connected to the first and second gate electrodes, respectively.

    Semiconductor device
    25.
    发明申请
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号：US20060081919A1

    公开(公告)日：2006-04-20

    申请号：US11044065

    申请日：2005-01-28

    申请人： Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

    发明人： Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

    IPC分类号： H01L29/24

    CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66348

    摘要： A semiconductor device comprising: a first-conductivity-type base layer; a second-conductivity-type emitter layer formed on a first main surface of said first-conductivity-type base layer; a collector electrode formed in contact with a surface of said second-conductivity-type emitter layer; a second-conductivity-type base layer formed on a second main surface of said first-conductivity-type base layer; a plurality of trenches which extend through said second-conductivity-type base layer to reach a predetermined depth of said first-conductivity-type base layer, and has a longitudinal direction in one direction; a gate electrode formed in said trench via a gate insulating film; a first-conductivity-type emitter layer selectively formed in contact with side walls of said trench, in a surface portion of said second-conductivity-type base layer; an emitter electrode formed in contact with a surface of said second-conductivity-type base layer and a surface of said first-conductivity-type emitter layer; and a second-conductivity-type semiconductor layer selectively formed in a region along the longitudinal direction of said trench, near the surface of said first-conductivity-type emitter layer.

    摘要翻译： 一种半导体器件，包括：第一导电型基底层; 形成在所述第一导电型基底层的第一主表面上的第二导电型发射极层; 与所述第二导电型发射极层的表面接触地形成的集电极; 形成在所述第一导电型基底层的第二主表面上的第二导电型基底层; 多个沟槽，其延伸穿过所述第二导电型基底层，以达到所述第一导电型基底层的预定深度，并且在一个方向上具有纵向方向; 通过栅极绝缘膜形成在所述沟槽中的栅电极; 在所述第二导电型基底层的表面部分中选择性地形成为与所述沟槽的侧壁接触的第一导电型发射极层; 与所述第二导电型基极层的表面和所述第一导电型发射极层的表面接触形成的发射极; 以及在所述第一导电型发射极层的表面附近，沿着所述沟槽的纵向的区域选择性地形成的第二导电型半导体层。

    Semiconductor device
    26.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20050263852A1

    公开(公告)日：2005-12-01

    申请号：US10974810

    申请日：2004-10-28

    申请人： Tsuneo Ogura ,  Masakazu Yamaguchi ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

    发明人： Tsuneo Ogura ,  Masakazu Yamaguchi ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

    IPC分类号： H01L29/78 ,  H01L27/082 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/739

    CPC分类号： H01L29/1095 ,  H01L29/0834 ,  H01L29/7397

    摘要： A semiconductor device comprises a first base layer of a first conductivity type; a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers, and formed to be deeper than the second base layers; an emitter layer formed along the trench on a surface of the second base layers; a collector layer of the second conductivity type, provided on a second surface of the first base layer opposite to the first surface; an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated from the second base layers and the emitter layer by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being deeper than the second base layers and being electrically isolated from the emitter layer and the second base layers.

    摘要翻译： 半导体器件包括第一导电类型的第一基极层; 多个第二导电类型的第二基层，设置在所述第一基底层的第一表面的一部分上; 沟槽形成在第二基底层的每一侧上，并且形成为比第二基底层更深; 在所述第二基底层的表面上沿着所述沟槽形成的发射极层; 设置在与第一表面相对的第一基底层的第二表面上的第二导电类型的集电极层; 形成在所述沟槽的内壁上的绝缘膜，所述绝缘膜在所述沟槽的底部比在所述沟槽的侧表面上更厚; 形成在所述沟槽内并与所述第二基极层和所述发射极层通过所述绝缘膜隔离的栅电极; 以及设置在彼此相邻的第二基底层之间的空间部分，空间部分比第二基底层更深，并且与发射极层和第二基底层电隔离。

    Semiconductor device
    27.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06891224B2

    公开(公告)日：2005-05-10

    申请号：US10461345

    申请日：2003-06-16

    申请人： Tsuneo Ogura ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

    发明人： Tsuneo Ogura ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

    IPC分类号： H01L29/78 ,  H01L21/8228 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/76 ,  H01L29/94 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/062 ,  H01L31/072 ,  H01L31/109

    CPC分类号： H01L29/1095 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/7394 ,  H01L29/7397

    摘要： A semiconductor device includes: a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a well layer of a second conductivity type formed on the barrier layer; a trench formed from the surface of the well layer to such a depth as to reach a region in the vicinity of a junction surface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of the second conductivity type selectively formed in a surface portion of the well layer, a source layer of the first conductivity type selectively formed in the surface portion of the well layer so as to contact a side wall of the gate insulating film in the trench and the contact layer, and a first main electrode formed so as to contact the contact layer and the source layer, wherein assuming that a total sum of impurity densities in the region of the barrier layer between the trenches is Qn, the Qn has a relation of the following equation: Qn≧2×1012 cm−2.

    摘要翻译： 半导体器件包括：形成在第一导电类型的基底层，形成在基底层上的第一导电类型的势垒层，形成在阻挡层上的第二导电类型的阱层; 从阱层的表面形成的沟槽到达阻挡层和基底层之间的接合面附近的区域的深度，通过栅极绝缘膜形成在沟槽中的栅电极， 选择性地形成在阱层的表面部分中的第二导电类型的层，选择性地形成在阱层的表面部分中以与沟槽中的栅极绝缘膜的侧壁接触的第一导电类型的源极层 以及形成为与接触层和源极层接触的第一主电极，其中假设沟槽之间的势垒层的区域中的杂质浓度的总和为Qn，则Qn具有关系 具有以下等式：Qn> = 2×10×12

    Solid-state image sensing device
    28.
    发明授权
    Solid-state image sensing device 有权
    固态摄像装置

    公开(公告)号：US07372089B2

    公开(公告)日：2008-05-13

    申请号：US11369734

    申请日：2006-03-08

    申请人： Tomoki Inoue ,  Shinji Uya

    发明人： Tomoki Inoue ,  Shinji Uya

    IPC分类号： H01L31/062

    CPC分类号： H01L27/14893 ,  H01L27/14647

    摘要： A solid-state image sensing device provided with photoelectric conversion films stacked above a semiconductor substrate, comprising: first impurity regions as defined herein; second impurity regions as defined herein; signal charge reading regions as defined herein; and third impurity regions as defined herein.

    摘要翻译： 一种设置在半导体衬底上方的光电转换膜的固态摄像装置，包括：如本文所定义的第一杂质区; 如本文所定义的第二杂质区; 信号电荷读取区域; 和第三杂质区域。

    Semiconductor device
    29.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US07119379B2

    公开(公告)日：2006-10-10

    申请号：US10689608

    申请日：2003-10-22

    申请人： Hideaki Ninomiya ,  Tomoki Inoue

    发明人： Hideaki Ninomiya ,  Tomoki Inoue

    IPC分类号： H01L29/32 ,  H01L29/94 ,  H01L29/768 ,  H01L23/58

    CPC分类号： H01L29/404 ,  H01L29/0619 ,  H01L29/0692 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device disclosed herein comprises: a first base region which is of a first conductivity type; a second base region which is of a second conductivity type and which is selectively formed on a major surface of the first base region; a stopper region which is of a first conductivity type and which is formed on the major surface of the first base region, the stopper region being a predetermined distance away from the second base region and surrounding the second base region; and a ring region which is of a second conductivity type which is formed on the major surface of the first base region between the second base region and the stopper region, the ring region being spirally around the second base region and electrically connected to the second base region and the stopper region.