公开(公告)号：US08724296B2

公开(公告)日：2014-05-13

申请号：US12767953

申请日：2010-04-27

Applicant: Toru Ishikawa ,  Masayuki Fujita ,  Takeshi Sano ,  Gaku Harada

Inventor： Toru Ishikawa ,  Masayuki Fujita ,  Takeshi Sano ,  Gaku Harada

IPC: H01G9/02

CPC classification number: H01G9/15 ,  H01G9/0036 ,  H01G9/028

Abstract: To provide a solid electrolytic capacitor having a high capacitance and an excellent heat resistance. A solid electrolytic capacitor includes: an anode 2; a dielectric layer 3 provided on the surface of the anode 2; a first conductive polymer layer 4a provided on the dielectric layer 3; a second conductive polymer layer 4b provided on the first conductive polymer layer 4a; a third conductive polymer layer 4c provided on the second conductive polymer layer 4b; and a cathode layer provided on the third conductive polymer layer 4c, wherein the first conductive polymer layer 4a is made of a conductive polymer film formed by polymerizing pyrrole or a derivative thereof, the second conductive polymer layer 4b is made of a conductive polymer film formed by polymerizing thiophene or a derivative thereof, and the third conductive polymer layer 4c is made of a conductive polymer film formed by electropolymerizing pyrrole or a derivative thereof.

Abstract translation: 提供具有高电容和优异耐热性的固体电解电容器。 固体电解电容器包括：阳极2; 设置在阳极2的表面上的电介质层3; 设置在电介质层3上的第一导电聚合物层4a; 设置在第一导电聚合物层4a上的第二导电聚合物层4b; 设置在第二导电聚合物层4b上的第三导电聚合物层4c; 以及设置在第三导电聚合物层4c上的阴极层，其中第一导电聚合物层4a由通过吡咯或其衍生物聚合形成的导电聚合物膜制成，第二导电聚合物层4b由形成的导电聚合物膜 通过聚合噻吩或其衍生物，并且第三导电聚合物层4c由通过电聚合吡咯或其衍生物形成的导电聚合物膜制成。

公开(公告)号：US08699286B2

公开(公告)日：2014-04-15

申请号：US13067675

申请日：2011-06-20

Applicant: Toru Ishikawa

Inventor： Toru Ishikawa

IPC: G11C7/00

CPC classification number: H03L7/0802 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028

Abstract: A semiconductor device is provided with: a delay circuit including a first delay unit that has a plurality of differential first delay elements which are respectively connected in series, a plurality pairs of first contacts which are respectively provided between the plurality of first delay elements, and a first output circuit that outputs a first delayed signal corresponding to a pair of first contacts selected from among the plurality pairs of first contacts, on receiving a first selection signal; a second delay unit that receives the first delayed signal, and that includes a plurality of single-ended second delay elements which are respectively connected in series, a plurality of second contacts which are respectively provided between the plurality of second delay elements, and a second output circuit that outputs a second delayed signal corresponding to a second contact selected from among the plurality of second contacts, on receiving a second selection signal; and a control circuit that outputs each of the first and second selection signals.

Abstract translation: 半导体器件具有：延迟电路，包括具有分别串联连接的多个差分第一延迟元件的第一延迟单元，分别设置在多个第一延迟元件之间的多对第一触点和 第一输出电路，在接收到第一选择信号时，输出与从所述多对第一接点中选出的一对第一接点对应的第一延迟信号; 第二延迟单元，其接收第一延迟信号，并且包括分别串联连接的多个单端第二延迟元件，分别设置在多个第二延迟元件之间的多个第二触点，以及第二延迟单元 输出电路，其在接收到第二选择信号时输出与从所述多个第二触点中选择的第二触点相对应的第二延迟信号; 以及输出第一和第二选择信号中的每一个的控制电路。

公开(公告)号：US08593897B2

公开(公告)日：2013-11-26

申请号：US13028862

申请日：2011-02-16

Applicant: Kunihiko Kato ,  Toru Ishikawa

Inventor： Kunihiko Kato ,  Toru Ishikawa

IPC: G11C7/04

CPC classification number: G11C5/148 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  Y02D10/14

Abstract: A memory system includes a clock generation circuit, a memory device, and a controller. The memory device includes output circuits and a temperature sensor, the output circuits configured to output data at an output timing obtained based on a clock signal supplied from the clock generation circuit. The controller includes input circuits that receive the data outputted from the memory device at an input timing obtained based on a clock signal supplied from the clock generation circuit and a correction value setting circuit that adjusts the input timing based on a temperature value from the temperature sensor.

Abstract translation: 存储器系统包括时钟产生电路，存储器件和控制器。 所述存储装置包括输出电路和温度传感器，所述输出电路经配置以基于从所述时钟发生电路提供的时钟信号获得的输出定时输出数据。 该控制器包括输入电路，该输入电路基于从时钟发生电路提供的时钟信号获得的输入定时接收从存储器件输出的数据，以及校正值设置电路，其基于来自温度传感器的温度值调节输入定时 。

公开(公告)号：US20120320686A1

公开(公告)日：2012-12-20

申请号：US13593046

申请日：2012-08-23

Applicant: Yasushi Takahashi ,  Toru Ishikawa

Inventor： Yasushi Takahashi ,  Toru Ishikawa

IPC: G11C7/10

CPC classification number: G11C11/4096 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

Abstract: A system including a controller and a memory chip. The controller includes first and second selection signal terminals supplying first and second selection signals, respectively, multiple first data terminals and multiple second data terminals. The memory chip includes a semiconductor substrate, third and fourth selection signal terminals provided on the semiconductor substrate and electrically coupled to the first and second selection signal terminals of the controller, respectively. Multiple third data terminals are provided on the semiconductor substrate and electrically coupled to the first data terminals of the controller, respectively. Multiple fourth data terminals are provided on the semiconductor substrate and electrically coupled to the second data terminals of the controller, respectively. The first and third data terminals communicate first data in response to the first selection signal. The second and fourth data terminals communicate second data in response to the second selection signal.

Abstract translation: 一种包括控制器和存储器芯片的系统。 控制器包括分别提供第一和第二选择信号的第一和第二选择信号端，多个第一数据终端和多个第二数据终端。 存储器芯片包括半导体衬底，设置在半导体衬底上并分别电耦合到控制器的第一和第二选择信号端子的第三和第四选择信号端子。 多个第三数据端子分别设置在半导体衬底上并电连接到控制器的第一数据端。 多个第四数据端子分别设置在半导体衬底上并电连接到控制器的第二数据端。 第一和第三数据终端响应于第一选择信号来传送第一数据。 第二和第四数据终端响应于第二选择信号传送第二数据。

公开(公告)号：US20110317503A1

公开(公告)日：2011-12-29

申请号：US13067675

申请日：2011-06-20

Applicant: Toru Ishikawa

Inventor： Toru Ishikawa

IPC: G11C8/18

CPC classification number: H03L7/0802 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028

Abstract: A semiconductor device is provided with: a delay circuit including a first delay unit that has a plurality of differential first delay elements which are respectively connected in series, a plurality pairs of first contacts which are respectively provided between the plurality of first delay elements, and a first output circuit that outputs a first delayed signal corresponding to a pair of first contacts selected from among the plurality pairs of first contacts, on receiving a first selection signal; a second delay unit that receives the first delayed signal, and that includes a plurality of single-ended second delay elements which are respectively connected in series, a plurality of second contacts which are respectively provided between the plurality of second delay elements, and a second output circuit that outputs a second delayed signal corresponding to a second contact selected from among the plurality of second contacts, on receiving a second selection signal; and a control circuit that outputs each of the first and second selection signals.

Abstract translation: 半导体器件具有：延迟电路，包括具有分别串联连接的多个差分第一延迟元件的第一延迟单元，分别设置在多个第一延迟元件之间的多对第一触点和 第一输出电路，在接收到第一选择信号时，输出与从所述多对第一接点中选出的一对第一接点对应的第一延迟信号; 第二延迟单元，其接收第一延迟信号，并且包括分别串联连接的多个单端第二延迟元件，分别设置在多个第二延迟元件之间的多个第二触点，以及第二延迟单元 输出电路，其在接收到第二选择信号时输出与从所述多个第二触点中选择的第二触点相对应的第二延迟信号; 以及输出第一和第二选择信号中的每一个的控制电路。

公开(公告)号：US08035432B2

公开(公告)日：2011-10-11

申请号：US12603850

申请日：2009-10-22

Applicant: Hiroki Takahashi ,  Toru Ishikawa

Inventor： Hiroki Takahashi ,  Toru Ishikawa

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/087

Abstract: A DLL circuit includes a first phase comparing circuit that compares phases between an input clock signal and an output clock signal, a first delay circuit that delays the output clock signal, and a second phase comparing circuit that compares phases between the input clock signal and an output signal of the first delay circuit. A delay amount in the variable delay circuit is controlled based on a comparison result of the first phase comparing circuit and a comparison result of the second phase comparing circuit.

Abstract translation: DLL电路包括：第一相位比较电路，其比较输入时钟信号和输出时钟信号之间的相位，延迟输出时钟信号的第一延迟电路;以及第二相位比较电路，其比较输入时钟信号和 第一延迟电路的输出信号。 基于第一相位比较电路的比较结果和第二相位比较电路的比较结果来控制可变延迟电路中的延迟量。

公开(公告)号：US07835220B2

公开(公告)日：2010-11-16

申请号：US12033657

申请日：2008-02-19

Applicant: Toru Ishikawa

Inventor： Toru Ishikawa

IPC: G11C8/18

CPC classification number: H03L7/0895 ,  H03L7/099 ,  H03L7/0995 ,  H03L2207/06

Abstract: A PLL circuit includes a phase comparator for outputting a frequency control signal based on a result of comparison between phases of an input reference clock signal and a fed-back oscillation signal; an oscillation circuit, connected to the phase comparator, for outputting an oscillation signal having a frequency in accordance with the frequency control signal, a power source voltage, and a predetermined reference voltage; and a bias control circuit, connected to the oscillation circuit, for increasing either the potential difference between the reference voltage of the oscillation circuit and a ground voltage or the potential difference between the power source voltage of the oscillation circuit and the ground voltage. A transistor in the oscillation circuit can operate in a saturation area, thereby operating the PLL circuit at a high speed with a low power source voltage, without being easily affected by a variation in the temperature or other process conditions.

Abstract translation: PLL电路包括：相位比较器，用于基于输入参考时钟信号和反馈振荡信号的相位之间的比较结果输出频率控制信号; 连接到所述相位比较器的振荡电路，用于输出具有与所述频率控制信号相对应的频率的振荡信号，电源电压和预定参考电压; 以及连接到振荡电路的偏置控制电路，用于增加振荡电路的参考电压与接地电压之间的电位差或振荡电路的电源电压与接地电压之间的电位差。 振荡电路中的晶体管可以在饱和区域中工作，从而以较低的电源电压高速运行PLL电路，而不会受到温度变化或其他工艺条件的影响。

公开(公告)号：US20100123499A1

公开(公告)日：2010-05-20

申请号：US12619396

申请日：2009-11-16

Applicant: Hiroki TAKAHASHI ,  Toru Ishikawa

Inventor： Hiroki TAKAHASHI ,  Toru Ishikawa

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  G11C7/22 ,  G11C7/222 ,  H03L7/095

Abstract: An information system with an enhanced effect in reducing jitter with a short period. An input clock signal CLKi is output via a voltage-controlled delay circuit 14 as an output clock signal CLKo, and an amount of delay in the voltage-controlled delay circuit 14 is controlled based on the result of comparison of a phase of the input clock signal CLKi and that of the output clock signal CLKo. A phase correction circuit 21 receives the input clock signal CLKi and the output clock signal CLKo. If, after the DLL circuit has become locked, the input clock signal and the output clock signal are out of phase relative to each other, the phase correction circuit 21 corrects the phase of the input clock signal CLKi based on a phase of the output clock signal CLKo to output a signal to the variable delay circuit 14 (FIG. 1).

Abstract translation: 一种在短时间内减少抖动的增强效果的信息系统。 输入时钟信号CLKi经由电压控制延迟电路14输出作为输出时钟信号CLKo，并且基于输入时钟的相位比较的结果来控制压控延迟电路14的延迟量 信号CLKi和输出时钟信号CLKo的信号。 相位校正电路21接收输入时钟信号CLKi和输出时钟信号CLKo。 如果在DLL电路被锁定之后，输入时钟信号和输出时钟信号彼此相位不相位，则相位校正电路21基于输出时钟的相位校正输入时钟信号CLKi的相位 信号CLKo将信号输出到可变延迟电路14（图1）。

公开(公告)号：US20100102862A1

公开(公告)日：2010-04-29

申请号：US12603910

申请日：2009-10-22

Applicant: Hiroki TAKAHASHI ,  Toru Ishikawa

Inventor： Hiroki TAKAHASHI ,  Toru Ishikawa

IPC: H03L7/06

CPC classification number: H03L7/085 ,  H03L7/0812

Abstract: Jitter is stably reduced. An input clock signal (CLKi) is outputted as an output clock signal (CLKo) via a voltage controlled delay circuit (12), and in addition a delay amount in the voltage controlled delay circuit (12) is controlled based on a result of a phase comparison of the input clock signal (CLKi) and the output clock signal (CLKo). A phase comparison result judging circuit (15) adds up results of phase comparison of the input clock signal (CLKi) and the output clock signal (CLKo) over a prescribed time, and controls the delay amount based on a distribution of addition results.

Abstract translation: 抖动稳定减少。 通过电压控制延迟电路（12）将输入时钟信号（CLKi）作为输出时钟信号（CLKo）输出，另外根据电压控制延迟电路（12）的结果控制延迟量 输入时钟信号（CLKi）和输出时钟信号（CLKo）的相位比较。 相位比较结果判断电路（15）在规定时间内将输入时钟信号（CLKi）和输出时钟信号（CLKo）的相位比较结果相加，并根据加法结果的分布来控制延迟量。

公开(公告)号：US07692451B2

公开(公告)日：2010-04-06

申请号：US11710941

申请日：2007-02-27

Applicant: Toru Ishikawa

Inventor： Toru Ishikawa

IPC: H03K19/094

CPC classification number: H03K19/0185

Abstract: A pulse generation section generates a pulse which is at H-level for the predetermined period of time from the timing of the input signal DATA changing to L-level. A main output section outputs a signal of L-level with transistors P1, N1, and N2 turned ON, while the pulse generation section outputs a pulse. When the pulse falls, the transistors P1 and N1 are turned OFF, and a potential of an output node is held at L-level by resistors of a L-level holding section.

Abstract translation: 脉冲发生部从输入信号DATA变更为L电平的时刻起，在规定时间内生成处于H电平的脉冲。 主输出部分在晶体管P1，N1和N2导通时输出L电平的信号，而脉冲产生部分输出脉冲。 当脉冲下降时，晶体管P1和N1截止，输出节点的电位由L电平保持部分的电阻器保持在L电平。