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155 条记录 (耗时 0.035 秒)

    Systems and Methods for Securing a Digital Communications Link
    24.
    发明申请
    Systems and Methods for Securing a Digital Communications Link 有权
    用于保护数字通信链路的系统和方法

    公开(公告)号：US20090190756A1

    公开(公告)日：2009-07-30

    申请号：US12021668

    申请日：2008-01-29

    申请人： Robert Hardacker ,  Kenichi Kawasaki

    发明人： Robert Hardacker ,  Kenichi Kawasaki

    IPC分类号： H04N7/167

    CPC分类号： H04N19/85 ,  H04L25/08 ,  H04L27/0008 ,  H04N7/1675 ,  H04N21/2383 ,  H04N21/4382

    摘要： A digital data signal, such as a digital video signal, is intentionally pre-distorted before being sent over a network. In one embodiment, this pre-distortion may be performed in accordance with a pre-distortion pattern or algorithm which is shared with only intended receivers. The pre-distortion pattern may be used to vary the pre-distortion on a periodic basis, as frequently as on a symbol-by-symbol basis. The pre-distortion function may include distorting the phase and/or the amplitude of the digital signal's modulation.

    摘要翻译： 诸如数字视频信号的数字数据信号在通过网络发送之前有意地被预先失真。 在一个实施例中，该预失真可以根据仅与预期接收机共享的预失真模式或算法来执行。 可以使用预失真模式来周期性地改变预失真，如在逐个符号的基础上那样频繁地进行。 预失真功能可以包括使数字信号调制的相位和/或振幅失真。

    Sytem and method for standby mode in directional signal receiver
    25.
    发明申请
    Sytem and method for standby mode in directional signal receiver 失效
    定向信号接收机待机模式的方法和方法

    公开(公告)号：US20060178127A1

    公开(公告)日：2006-08-10

    申请号：US11054468

    申请日：2005-02-09

    申请人： Kenichi Kawasaki

    发明人： Kenichi Kawasaki

    IPC分类号： H04B1/16 ,  H04B1/38 ,  H04M1/00

    CPC分类号： H04W52/0245 ,  Y02D70/142

    摘要： A wireless receiver of a directional signal such as a 60 GHz signal can have a low power standby mode in which the linear oscillator (radio) portion of the receiver is deenergized. A DC detect circuit can detect the DC portion of an incoming signal, at which time the DC detect circuit energizes the remaining portions of the receiver.

    摘要翻译： 诸如60GHz信号的定向信号的无线接收机可以具有低功率待机模式，其中接收机的线性振荡器（无线电）部分被断电。 DC检测电路可以检测输入信号的DC部分，此时DC检测电路为接收器的剩余部分通电。

    Semiconductor device, method of testing the semiconductor device, and semiconductor integrated circuit
    26.
    发明授权
    Semiconductor device, method of testing the semiconductor device, and semiconductor integrated circuit 有权
    半导体器件，半导体器件的测试方法以及半导体集成电路

    公开(公告)号：US06774655B2

    公开(公告)日：2004-08-10

    申请号：US10622472

    申请日：2003-07-21

    申请人： Yasurou Matsuzaki ,  Masao Nakano ,  Toshiya Uchida ,  Atsushi Hatakeyama ,  Kenichi Kawasaki ,  Yasuhiro Fujii

    发明人： Yasurou Matsuzaki ,  Masao Nakano ,  Toshiya Uchida ,  Atsushi Hatakeyama ,  Kenichi Kawasaki ,  Yasuhiro Fujii

    IPC分类号： G01R3102

    CPC分类号： G11C29/022 ,  G11C29/02

    摘要： A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode. A method of testing the semiconductor device and a semiconductor integrated circuit, having the test circuit, are also disclosed.

    摘要翻译： 公开了一种安装在板等上并具有测试电路的半导体器件，具有在半导体端子上以低成本进行接触测试的功能。 半导体器件包括用于测试外部端子和测试模式控制电路单元的接触状态的端子测试电路。 测试模式控制电路单元在施加电源电压时输出指示第一操作模式的信号，响应于输入到诸如芯片选择端子的特定终端的控制信号，向终端测试电路输出测试模式信号 并且响应于输入到特定终端的控制信号的电平改变的次数而输出指示第二操作模式的信号。 优选地，第一操作模式是终端测试模式，并且第二操作模式是正常操作模式。 还公开了一种测试半导体器件的方法和具有测试电路的半导体集成电路。

    Semiconductor device, method of testing the semiconductor device, and semiconductor integrated circuit
    27.
    发明授权
    Semiconductor device, method of testing the semiconductor device, and semiconductor integrated circuit 有权
    半导体器件，半导体器件的测试方法以及半导体集成电路

    公开(公告)号：US06621283B1

    公开(公告)日：2003-09-16

    申请号：US09437221

    申请日：1999-11-10

    申请人： Yasurou Matsuzaki ,  Masao Nakano ,  Toshiya Uchida ,  Atsushi Hatakeyama ,  Kenichi Kawasaki ,  Yasuhiro Fujii

    发明人： Yasurou Matsuzaki ,  Masao Nakano ,  Toshiya Uchida ,  Atsushi Hatakeyama ,  Kenichi Kawasaki ,  Yasuhiro Fujii

    IPC分类号： G01R3102

    CPC分类号： G11C29/022 ,  G11C29/02

    摘要： A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode. A method of testing the semiconductor device and a semiconductor integrated circuit, having the test circuit, are also disclosed.

    摘要翻译： 公开了一种安装在板等上并具有测试电路的半导体器件，具有在半导体端子上以低成本进行接触测试的功能。 半导体器件包括用于测试外部端子和测试模式控制电路单元的接触状态的端子测试电路。 测试模式控制电路单元在施加电源电压时输出指示第一操作模式的信号，响应于输入到诸如芯片选择端子的特定终端的控制信号，向终端测试电路输出测试模式信号 并且响应于输入到特定终端的控制信号的电平改变的次数而输出指示第二操作模式的信号。 优选地，第一操作模式是终端测试模式，并且第二操作模式是正常操作模式。 还公开了一种测试半导体器件的方法和具有测试电路的半导体集成电路。

    Braking device for dual-bearing reel
    29.
    发明授权
    Braking device for dual-bearing reel 有权
    双轴承卷轴制动装置

    公开(公告)号：US06293483B1

    公开(公告)日：2001-09-25

    申请号：US09610584

    申请日：2000-07-05

    申请人： Jun Sato ,  Kenichi Kawasaki

    发明人： Jun Sato ,  Kenichi Kawasaki

    IPC分类号： A01K8902

    CPC分类号： A01K89/0155

    摘要： A dual-bearing reel centrifugal braking mechanism 23 that enables braking force to be adjusted readily and accurately. The centrifugal braking mechanism 2, for braking the spool 12 rotatively provided in a reel unit 1, and includes a brake element 51, a rotor 52, a plurality of shifting members 53, and a shifting mechanism 54. The brake element 51 is fixed to the reel body. The rotor 52 is disposed being concentric with the brake element 51. The rotor 52 is a member which rotates together with the spool 12 and is capable of moving in a direction along the axial direction of the spool 12 with respect of the reel unit 1. The plurality of shifting members 53 is attached to the rotor 52 in a movable manner so that each member may be moved towards the brake element 51 by a centrifugal force generated by the rotation of the spool 12. The plurality of shifting members 53 is also members which are capable of making contact with the brake element 51 with a different number of them during a braking operation by the movement of the rotor 52 in the axial direction. The shifting mechanism 54 is a mechanism for reciprocating the rotor 52 in the axial direction.

    摘要翻译： 双轴承卷轴离心制动机构23，其能够容易且精确地调节制动力。 离心式制动机构2用于制动旋转地设置在卷轴单元1中的线轴12，并且包括制动元件51，转子52，多个变速构件53和变速机构54.制动元件51固定到 卷轴体。 转子52设置成与制动元件51同心。转子52是与卷轴12一起旋转的构件，并且能够相对于卷轴单元1沿着卷轴12的轴向方向移动。 多个移动构件53以可移动的方式附接到转子52，使得每个构件可以通过由卷轴12的旋转产生的离心力而朝向制动元件51移动。多个移动构件53也是构件 其能够通过转子52沿轴向的移动而在制动操作期间与不同数量的制动元件51接触。 换档机构54是使转子52沿轴向往复运动的机构。

    Semiconductor integrated circuit with appropriate data output timing and reduced power consumption
    30.
    发明授权
    Semiconductor integrated circuit with appropriate data output timing and reduced power consumption 失效
    半导体集成电路具有适当的数据输出时序，降低功耗

    公开(公告)号：US5955904A

    公开(公告)日：1999-09-21

    申请号：US931669

    申请日：1997-09-17

    申请人： Kenichi Kawasaki

    发明人： Kenichi Kawasaki

    IPC分类号： G11C11/407 ,  G06F1/10 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/4096 ,  H03K5/13 ,  H03K19/0175 ,  H03L7/081 ,  H04L7/033 ,  H03L7/00

    CPC分类号： H03L7/0805 ,  G11C11/4076 ,  G11C11/4096 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/22 ,  H03L7/0814

    摘要： A semiconductor integrated circuit includes a first clock-input circuit receiving an external clock from an external source and outputting an internal clock, an output-control-clock generating circuit receiving the internal clock to generate an output-control clock, and a first data-output circuit outputting output data in synchronism with one of a rise timing and a fall timing of the output-control clock. The output-control-clock generating circuit controls a timing of the output-control clock such that the first data-output circuit outputs the output data a predetermined fraction of one clock cycle of the external clock after a clock pulse of the external clock.

    摘要翻译： 半导体集成电路包括：第一时钟输入电路，从外部源接收外部时钟并输出内部时钟;输出控制时钟发生电路，接收所述内部时钟以产生输出控制时钟;以及第一数据 - 输出电路与输出控制时钟的上升定时和下降定时中的一个同步地输出输出数据。 输出控制时钟发生电路控制输出控制时钟的定时，使得第一数据输出电路在外部时钟的时钟脉冲之后输出外部时钟的一个时钟周期的预定分数。