公开(公告)号：US11616035B2

公开(公告)日：2023-03-28

申请号：US17397765

申请日：2021-08-09

Applicant: United Microelectronics Corp.

Inventor： Teng-Chuan Hu ,  Chun-Hung Chen ,  Chu-Fu Lin

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18

Abstract: A semiconductor structure, including a substrate and multiple chips, is provided. The chips are stacked on the substrate. Each of the chips has a first side and a second side opposite to each other. Each of the chips includes a transistor adjacent to the first side and a storage node adjacent to the second side. Two adjacent chips are bonded to each other. The transistor of one of the two adjacent chips is electrically connected to the storage node of the other one of the two adjacent chips to form a memory cell.

公开(公告)号：US20230025541A1

公开(公告)日：2023-01-26

申请号：US17397765

申请日：2021-08-09

Applicant: United Microelectronics Corp.

Inventor： Teng-Chuan Hu ,  Chun-Hung Chen ,  Chu-Fu Lin

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor structure, including a substrate and multiple chips, is provided. The chips are stacked on the substrate. Each of the chips has a first side and a second side opposite to each other. Each of the chips includes a transistor adjacent to the first side and a storage node adjacent to the second side. Two adjacent chips are bonded to each other. The transistor of one of the two adjacent chips is electrically connected to the storage node of the other one of the two adjacent chips to form a memory cell.

公开(公告)号：US10340231B2

公开(公告)日：2019-07-02

申请号：US15486521

申请日：2017-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Chu-Fu Lin ,  Ming-Tse Lin

IPC: H01L23/64 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.

公开(公告)号：US20180269167A1

公开(公告)日：2018-09-20

申请号：US15486521

申请日：2017-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Chu-Fu Lin ,  Ming-Tse Lin

IPC: H01L23/64 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/645 ,  H01L21/568 ,  H01L23/3185 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/96 ,  H01L2924/1431 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/30107

Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.

公开(公告)号：US20170221796A1

公开(公告)日：2017-08-03

申请号：US15011433

申请日：2016-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chu-Fu Lin ,  Ming-Tse Lin ,  Kuei-Sheng Wu

IPC: H01L23/48 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: A TSV structure includes a substrate comprising at least a TSV opening formed therein, a conductive layer disposed in the TSV opening, and a bi-layered liner disposed in between the substrate and the conductive layer. More important, the bi-layered liner includes a first liner and a second liner, and a Young's modulus of the first liner is different from a Young's modulus of the second liner.

公开(公告)号：US20140291801A1

公开(公告)日：2014-10-02

申请号：US13854142

申请日：2013-04-01

Applicant: United Microelectronics CORP.

Inventor： Chu-Fu Lin ,  Chien-Li Kuo ,  Ching-Li Yang

IPC: H01L23/525 ,  H01L23/00

CPC classification number: H01L23/5252 ,  H01L23/525 ,  H01L23/5254 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of programming an anti-fuse includes steps as follows. First, an insulating layer is provided. An anti-fuse region is defined on the insulating layer. An anti-fuse is embedded within the anti-fuse region of the insulating layer. The anti-fuse includes at least a first conductor and a second conductor. Then, part of the insulating layer is removed by a laser to form an anti-fuse opening in the insulating layer. Part of the first conductor and part of the second conductor are exposed through the anti-fuse opening. After that, a under bump metallurgy layer is formed in the anti-fuse opening to connect the first conductor and the second conductor electrically.

Abstract translation: 反熔丝编程方法包括以下步骤。 首先，提供绝缘层。 在绝缘层上限定反熔丝区域。 反熔丝嵌入在绝缘层的反熔丝区域内。 反熔丝包括至少第一导体和第二导体。 然后，通过激光去除绝缘层的一部分，以在绝缘层中形成抗熔丝开口。 第一导体的一部分和第二导体的一部分通过反熔丝开口露出。 之后，在反熔丝开口中形成凸起下的金属层，以电连接第一导体和第二导体。

公开(公告)号：US20140145326A1

公开(公告)日：2014-05-29

申请号：US13689727

申请日：2012-11-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chu-Fu Lin ,  Ming-Tse Lin ,  Yung-Chang Lin

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/525 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/00

Abstract: A substrate with integrated passive devices and method of manufacturing the same are presented. The substrate may include through silicon vias, at least one redistribution layer having a 1st passive device pattern and stacked vias, and an under bump metal layer having a 2nd passive device pattern.

Abstract translation: 提出了具有集成无源器件的基板及其制造方法。 衬底可以包括通过硅通孔，具有第一无源器件图案和堆叠通孔的至少一个再分布层，以及具有第二无源器件图案的下凸块金属层。