公开(公告)号：US20150179580A1

公开(公告)日：2015-06-25

申请号：US14139879

申请日：2013-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo ,  Chun-Hung Chen ,  Yung-Chang Lin ,  Ming-Tse Lin

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating hybrid interconnect structure is disclosed. The method includes the steps of: providing a material layer; forming a through-silicon hole in the material layer; forming a patterned resist on the material layer, wherein the patterned resist comprises at least an opening for exposing the through-silicon hole; and forming a conductive layer to fill the through-silicon hole and the opening in the patterned resist.

Abstract translation: 公开了一种用于制造混合互连结构的方法。 该方法包括以下步骤：提供材料层; 在所述材料层中形成通孔; 在所述材料层上形成图案化的抗蚀剂，其中所述图案化的抗蚀剂至少包括用于暴露所述通孔的孔; 以及形成导电层以填充图案化的抗蚀剂中的通孔和孔。

公开(公告)号：US09035457B2

公开(公告)日：2015-05-19

申请号：US13689727

申请日：2012-11-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chu-Fu Lin ,  Ming-Tse Lin ,  Yung-Chang Lin

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/14 ,  H01L23/498 ,  H01L23/525 ,  H01L23/522

CPC classification number: H01L24/11 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/525 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/00

Abstract: A substrate with integrated passive devices and method of manufacturing the same are presented. The substrate may include through silicon vias, at least one redistribution layer having a 1st passive device pattern and stacked vias, and an under bump metal layer having a 2nd passive device pattern.

Abstract translation: 提出了具有集成无源器件的基板及其制造方法。 衬底可以包括通过硅通孔，具有第一无源器件图案和堆叠通孔的至少一个再分布层，以及具有第二无源器件图案的下凸块金属层。

公开(公告)号：US20150061151A1

公开(公告)日：2015-03-05

申请号：US14016330

申请日：2013-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo ,  Yung-Chang Lin ,  Ming-Tse Lin

IPC: H01L23/522

CPC classification number: H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A package structure having silicon through vias connected to ground potential is disclosed, comprising a first device, a second device and a conductive adhesive disposed between the first device and the second device. The first device comprises a substrate having a front surface and a back surface, and a plurality of through silicon vias filled with a conductor formed within the substrate. The first device is externally connected to the second device by wire bonding.

Abstract translation: 公开了一种具有连接到地电势的硅通孔的封装结构，包括设置在第一器件和第二器件之间的第一器件，第二器件和导电粘合剂。 第一器件包括具有前表面和后表面的衬底以及填充有形成在衬底内的导体的多个通孔硅通孔。 第一器件通过引线接合外部连接到第二器件。

公开(公告)号：US09343359B2

公开(公告)日：2016-05-17

申请号：US14140523

申请日：2013-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Ming-Tse Lin ,  Yung-Chang Lin ,  Chien-Li Kuo

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L23/525

CPC classification number: H01L21/76879 ,  H01L21/76846 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L23/53238 ,  H01L24/02 ,  H01L2224/023 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02315 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/05548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating integrated structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon hole in the substrate; forming a patterned resist on the substrate, wherein the patterned resist comprises at least one opening corresponding to a redistribution layer (RDL) pattern and exposing the through-silicon hole and at least another opening corresponding to another redistribution layer (RDL) pattern and connecting to the at least one opening; and forming a conductive layer to fill the through-silicon hole, the at least one opening and the at least another opening in the patterned resist so as to form a through-silicon via, a through-silicon via RDL pattern and another RDL pattern in one structure.

Abstract translation: 公开了一种制造一体化结构的方法。 该方法包括以下步骤：提供衬底; 在所述基板中形成贯通硅孔; 在衬底上形成图案化的抗蚀剂，其中所述图案化抗蚀剂包括对应于再分布层（RDL）图案的至少一个开口，并暴露所述穿硅孔和至少另一个对应于另一再分布层（RDL）图案的开口，并连接到 所述至少一个开口; 以及形成导电层以填充图案化的抗蚀剂中的通孔，至少一个开口和至少另一个开口，以便形成贯穿硅通孔，穿硅通孔RDL图案和另一RDL图案 一个结构。

公开(公告)号：US20150311117A1

公开(公告)日：2015-10-29

申请号：US14791265

申请日：2015-07-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Tse Lin ,  Chu-Fu Lin ,  Chien-Li Kuo ,  Yung-Chang Lin

IPC: H01L21/768 ,  H01L23/00 ,  H01L21/302 ,  H01L21/283

CPC classification number: H01L21/76898 ,  H01L21/283 ,  H01L21/302 ,  H01L21/7685 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76883 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/16 ,  H01L28/60 ,  H01L2224/02317 ,  H01L2224/0401 ,  H01L2224/4824 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening.

Abstract translation: 本发明提供一种用TSV电极形成芯片的方法。 提供具有第一表面和第二表面的基底。 从第二表面的一侧进行变薄处理，使得第二表面变成第三表面。 接下来，在衬底中形成穿过第一表面和第三表面的穿透。 图案化材料层形成在衬底上，其中图案化材料层具有开口以暴露穿透通孔。 导电层形成在第三表面上，从而同时在穿透孔中形成TSV电极和开口中的表面导电层。

公开(公告)号：US09048223B2

公开(公告)日：2015-06-02

申请号：US14016330

申请日：2013-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo ,  Yung-Chang Lin ,  Ming-Tse Lin

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A package structure having silicon through vias connected to ground potential is disclosed, comprising a first device, a second device and a conductive adhesive disposed between the first device and the second device. The first device comprises a substrate having a front surface and a back surface, and a plurality of through silicon vias filled with a conductor formed within the substrate. The first device is externally connected to the second device by wire bonding.

Abstract translation: 公开了一种具有连接到地电势的硅通孔的封装结构，包括设置在第一器件和第二器件之间的第一器件，第二器件和导电粘合剂。 第一器件包括具有前表面和后表面的衬底以及填充有形成在衬底内的导体的多个通孔硅通孔。 第一器件通过引线接合外部连接到第二器件。

公开(公告)号：US20160133518A1

公开(公告)日：2016-05-12

申请号：US14997594

申请日：2016-01-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo ,  Yung-Chang Lin

IPC: H01L21/768 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L21/76898 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/481 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination.

Abstract translation: 半导体器件包括衬底; 设置在所述基板上的层间电介质; 穿透底物和ILD的TSV。 此外，在衬底中设置多个浅沟槽隔离（STI），并且屏蔽环设置在围绕STI上的TSV的ILD中。 在形成TSV的过程中，接触环可以保护邻近部件免受金属污染。

公开(公告)号：US09287173B2

公开(公告)日：2016-03-15

申请号：US13900565

申请日：2013-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo ,  Chun-Hung Chen ,  Ming-Tse Lin ,  Yung-Chang Lin

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through silicon via includes a substrate and a conductive plug. The substrate has a hole in a side. The conductive plug is disposed in the hole, and the conductive plug having an upper part protruding from the side, wherein the upper part has a top part and a bottom part, and the top part is finer than the bottom part. Moreover, a through silicon via process formed said through silicon via is also provided, which includes the following step. A hole is formed in a substrate from a side. A first conductive material is formed to cover the hole and the side. A patterned photoresist is formed to cover the side but exposing the hole. A second conductive material is formed on the exposed first conductive material. The patterned photoresist is removed. The first conductive material on the side is removed to form a conductive plug in the hole.

Abstract translation: 透硅通孔包括基底和导电塞。 基板在一侧具有孔。 导电插头设置在孔中，导电插头具有从侧面突出的上部，其中上部具有顶部和底部，并且顶部比底部更细。 此外，还提供了通过硅通孔形成的贯穿硅通孔工艺，其包括以下步骤。 从一侧在基板上形成孔。 形成第一导电材料以覆盖孔和侧面。 形成图案化的光致抗蚀剂以覆盖侧面但暴露孔。 在暴露的第一导电材料上形成第二导电材料。 去除图案化的光致抗蚀剂。 去除侧面上的第一导电材料以在孔中形成导电塞。

公开(公告)号：US20150014828A1

公开(公告)日：2015-01-15

申请号：US13939184

申请日：2013-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo ,  Yung-Chang Lin ,  Ming-Tse Lin ,  Kuei-Sheng Wu ,  Chia-Fang Lin

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L23/481 ,  H01L23/535 ,  H01L23/585 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention provides a semiconductor device with a shielding structure. The semiconductor device includes a substrate, an RF circuit, a shielding structure and an interconnection system. The substrate includes an active side and a back side. The RF circuit is disposed on the active side of the substrate. The shielding structure is disposed on the active side and encompasses the RF circuit. The shielding structure is grounded. The shielding structure includes a shielding TST which does not penetrate through the substrate. The interconnection system is disposed on the active side of the substrate. The interconnection system includes a connecting unit electrically connect a signal to the RF circuit.

Abstract translation: 本发明提供一种具有屏蔽结构的半导体器件。 半导体器件包括衬底，RF电路，屏蔽结构和互连系统。 基板包括有源侧和背面。 RF电路设置在基板的有源侧。 屏蔽结构设置在有源侧并且包围RF电路。 屏蔽结构接地。 屏蔽结构包括不穿透基板的屏蔽TST。 互连系统设置在基板的有源侧。 互连系统包括将信号电连接到RF电路的连接单元。

公开(公告)号：US20140145326A1

公开(公告)日：2014-05-29

申请号：US13689727

申请日：2012-11-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chu-Fu Lin ,  Ming-Tse Lin ,  Yung-Chang Lin

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/525 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/00

Abstract: A substrate with integrated passive devices and method of manufacturing the same are presented. The substrate may include through silicon vias, at least one redistribution layer having a 1st passive device pattern and stacked vias, and an under bump metal layer having a 2nd passive device pattern.

Abstract translation: 提出了具有集成无源器件的基板及其制造方法。 衬底可以包括通过硅通孔，具有第一无源器件图案和堆叠通孔的至少一个再分布层，以及具有第二无源器件图案的下凸块金属层。