公开(公告)号：US12290005B2

公开(公告)日：2025-04-29

申请号：US18679437

申请日：2024-05-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yu-Ping Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Si-Han Tsai ,  Che-Wei Chang ,  Jing-Yin Jhang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/85 ,  H10N50/01

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

公开(公告)号：US12289900B2

公开(公告)日：2025-04-29

申请号：US17335049

申请日：2021-05-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsiao Chen ,  Kai-Lin Lee ,  Wei-Jen Chen

IPC: H10D30/47 ,  H10D30/01 ,  H10D62/85

Abstract: A high electron mobility transistor includes a substrate. A channel layer is disposed on the substrate. An active layer is disposed on the channel layer. The active layer includes a P-type aluminum gallium nitride layer. A P-type gallium nitride gate is disposed on the active layer. A source electrode and a drain electrode are disposed on the active layer.

公开(公告)号：US12288818B2

公开(公告)日：2025-04-29

申请号：US18128234

申请日：2023-03-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zong-Han Lin ,  Yi-Han Ye

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

Abstract: A lateral diffusion metal oxide semiconductor (LDMOS) device includes a first fin-shaped structure on a substrate, a shallow trench isolation (STI) adjacent to the first fin-shaped structure, a first gate structure on the first fin-shaped structure, a spacer adjacent to the first gate structure, and a contact field plate adjacent to the first gate structure and directly on the STI. Preferably, a sidewall of the spacer is aligned with a sidewall of the first fin-shaped structure.

公开(公告)号：US20250133755A1

公开(公告)日：2025-04-24

申请号：US18498049

申请日：2023-10-31

Applicant: United Microelectronics Corp.

Inventor： Shin-Hung Li

IPC: H01L21/02 ,  H01L21/768

Abstract: Provided are a capacitor device and a manufacturing method thereof. The capacitor device includes a first electrode, a second electrode, an insulating layer, a first dielectric layer, a second dielectric layer, a third electrode and a fourth electrode. The first electrode is disposed on a substrate. The second electrode is disposed on the first electrode. The insulating layer is disposed between the first electrode and the second electrode. The first dielectric layer is disposed on the substrate and covers the first electrode, the second electrode and the insulating layer. The second dielectric layer is disposed on the first dielectric layer. The third electrode and the fourth electrode are disposed in the second dielectric layer and separated from each other. The third electrode is electrically connected to the first electrode, and the fourth electrode is electrically connected to the second electrode.

公开(公告)号：US20250132168A1

公开(公告)日：2025-04-24

申请号：US18513669

申请日：2023-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ching Chen ,  Ching-Ling Lin ,  Wen-An Liang

IPC: H01L21/3213 ,  H01L21/3205 ,  H01L21/321 ,  H01L29/66

Abstract: A planarization method includes the following steps. A silicon layer is deposited on a substrate, and a top surface of the silicon layer includes a lower portion and a bump portion protruding upwards from the lower portion. An ion bombardment etching process is performed to the silicon layer for reducing a surface step height of the silicon layer. The top surface of the silicon layer is etched by the ion bombardment etching process to become a post-etching top surface, and a distance between a topmost portion of the post-etching top surface and a bottommost portion of the post-etching top surface in a vertical direction is less than a distance between a topmost portion of the bump portion and the lower portion in the vertical direction before the ion bombardment etching process. Subsequently, a chemical mechanical polishing process is performed to the post-etching top surface of the silicon layer.

公开(公告)号：US12283329B2

公开(公告)日：2025-04-22

申请号：US18306221

申请日：2023-04-24

Applicant: United Microelectronics Corp.

Inventor： Chia Wei Ho ,  Min Chia Wang ,  Chung Ming Lin ,  Jin Pang Chi

IPC: G11C17/18 ,  G11C17/16 ,  H03K17/687

Abstract: A power circuit is adapted for providing a programming voltage to an electronic fuse circuit, and includes a pass transistor of a P-type metal-oxide-semiconductor transistor, a buffer circuit, and a bulk voltage control circuit. The pass transistor includes a bulk electrode, a gate electrode, a first source/drain electrode receiving a system high voltage, and a second source/drain electrode connected to a bit line. The buffer circuit provides a control voltage to the gate electrode of the pass transistor. The pass transistor is turned on during a programming operation and turned off during a reading operation. The bulk voltage control circuit independently provides a bulk voltage to the bulk electrode. A last-stage buffer of the buffer circuit is also activated by the bulk voltage to control the pass transistor during the reading operation of the electronic fuse circuit. A method for providing power to an electronic fuse circuit is also provided.

公开(公告)号：US20250125252A1

公开(公告)日：2025-04-17

申请号：US18516868

申请日：2023-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Chia Yang ,  Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L23/522 ,  H01L21/768

Abstract: A semiconductor device includes a device layer, an interlayer dielectric layer disposed above the device layer, a first interconnection structure, a second interconnection structure, and a first dielectric layer. The interlayer dielectric layer includes a first portion and a second portion disposed above a first device region and a second device region, respectively. A top surface of the first portion is lower than a top surface of the second portion in a vertical direction. The first interconnection structure includes first conductive lines partly located in the first portion. The second interconnection structure includes second conductive lines located in the second portion. The first dielectric layer is disposed on the first portion, a part of the first dielectric layer is sandwiched between two adjacent first conductive lines, and a bottom surface of the first dielectric layer is lower than the top surface of the second portion in the vertical direction.

公开(公告)号：US12279536B2

公开(公告)日：2025-04-15

申请号：US18610212

申请日：2024-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Yen-Tsai Yi ,  Hsiang-Wen Ke

IPC: H10N50/80 ,  G11C11/16 ,  H10N50/01 ,  H10N50/85 ,  H01F10/32 ,  H01F41/32

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.

公开(公告)号：US12279535B2

公开(公告)日：2025-04-15

申请号：US18511984

申请日：2023-11-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Ya-Sheng Feng

IPC: H10N50/80 ,  H01L21/768 ,  H10N50/01

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; removing the sacrificial layer to form a recess; forming a barrier layer and a free layer in the recess; forming a top electrode layer on the free layer; and patterning the top electrode layer and the free layer to form a second MTJ.

公开(公告)号：US12279446B2

公开(公告)日：2025-04-15

申请号：US18645366

申请日：2024-04-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Ruei-Jhe Tsao ,  Che-Hua Chang

IPC: H10D30/66 ,  H10D30/67

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first drift region, a first source/drain region, and a gate oxide layer. The gate structure and the gate oxide layer are disposed on the semiconductor substrate. The first drift region is disposed in the semiconductor substrate. The first source/drain region is disposed in the first drift region. At least a part of a first portion of the gate oxide layer is disposed between the gate structure and the semiconductor substrate in a vertical direction. A second portion of the gate oxide layer is disposed between the first portion and the first source/drain region in a horizontal direction. The second portion includes a bottom extending downwards and a first depressed top surface located above the bottom. A part of the first drift region is located under the first portion and the second portion of the gate oxide layer.