公开(公告)号：US12154981B2

公开(公告)日：2024-11-26

申请号：US18134582

申请日：2023-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, and a gate electrode. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer, where the surface of the semiconductor barrier layer includes at least one recess. The gate electrode is disposed on the semiconductor barrier layer and includes a body portion and at least one vertical extension portion overlapping the recess.

公开(公告)号：US12034055B2

公开(公告)日：2024-07-09

申请号：US18081646

申请日：2022-12-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/778

CPC classification number: H01L29/41775 ,  H01L29/0607 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, a first electrode, a second electrode, a first dielectric layer and a second dielectric layer. The semiconductor channel layer is disposed on the substrate. The semiconductor barrier layer is disposed on the semiconductor channel layer. The gate electrode is disposed on the semiconductor barrier layer. The first electrode is disposed at one side of the gate electrode. The first electrode includes a body portion and a vertical extension portion. The second electrode is disposed at another side of the gate electrode. The second electrode includes a body portion and a vertical extension portion. The first dielectric layer is disposed between the vertical extension portion of the first electrode and the semiconductor channel layer. The second dielectric layer is disposed between the vertical extension portion of the second electrode and the semiconductor channel layer.

公开(公告)号：US20240178067A1

公开(公告)日：2024-05-30

申请号：US18432087

申请日：2024-02-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L21/78 ,  H01L23/544

CPC classification number: H01L21/78 ,  H01L23/544

Abstract: A manufacturing method of a semiconductor device includes the following steps. A singulation process is performed to a semiconductor wafer for forming semiconductor dies and includes a first cutting step, a thinning step, and a second cutting step. The first cutting step is configured to form first openings in the semiconductor wafer by etching. A portion of the semiconductor wafer is located between each first opening and a back surface and removed by the thinning step. Each first opening penetrates through the semiconductor wafer after the thinning step. The second cutting step is configured to form second openings. Each second opening penetrates through the semiconductor wafer for separating the semiconductor dies. A semiconductor die includes two first side surfaces opposite to each other and two second side surfaces opposite to each other. A roughness of each first side surface is different from a roughness of each second side surface.

公开(公告)号：US20240128317A1

公开(公告)日：2024-04-18

申请号：US18522119

申请日：2023-11-28

Applicant: United Microelectronics Corp.

Inventor： Po-Yu Yang

IPC: H01L29/06 ,  H01L21/322 ,  H01L27/12 ,  H01L29/10 ,  H01L29/24 ,  H01L29/34

CPC classification number: H01L29/0665 ,  H01L21/3226 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/24 ,  H01L29/34

Abstract: A silicon on insulator (SOI) device includes a wafer and a trap-rich layer. The wafer includes a top silicon layer disposed on a buried oxide layer. The trap-rich layer having nano-dots and an oxide layer are stacked on a high resistivity substrate sequentially, wherein the oxide layer is bonded with the buried oxide layer. Or, a silicon on insulator (SOI) device includes a wafer and a high resistivity substrate. The wafer includes a top silicon layer disposed on a buried oxide layer. The high resistivity substrate is bonded with the buried oxide layer, wherein a positive fixed charge layer is induced at a surface of the buried oxide layer contacting the high resistivity substrate, and a doped negative charge layer is right next to the positive fixed charge layer. The present invention also provides a method of forming said silicon on insulator (SOI) device.

公开(公告)号：US11916139B2

公开(公告)日：2024-02-27

申请号：US17185979

申请日：2021-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/66462 ,  H01L29/7787

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, and a gate electrode. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer, where the surface of the semiconductor barrier layer includes at least one recess. The gate electrode is disposed on the semiconductor barrier layer and includes a body portion and at least one vertical extension portion overlapping the recess.

公开(公告)号：US11888025B2

公开(公告)日：2024-01-30

申请号：US17079552

申请日：2020-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/06 ,  H01L29/24 ,  H01L27/12 ,  H01L29/34 ,  H01L29/10 ,  H01L21/322

CPC classification number: H01L29/0665 ,  H01L21/3226 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/24 ,  H01L29/34

Abstract: A silicon on insulator (SOI) device includes a wafer and a trap-rich layer. The wafer includes a top silicon layer disposed on a buried oxide layer. The trap-rich layer having nano-dots and an oxide layer are stacked on a high resistivity substrate sequentially, wherein the oxide layer is bonded with the buried oxide layer. Or, a silicon on insulator (SOI) device includes a wafer and a high resistivity substrate. The wafer includes a top silicon layer disposed on a buried oxide layer. The high resistivity substrate is bonded with the buried oxide layer, wherein a positive fixed charge layer is induced at a surface of the buried oxide layer contacting the high resistivity substrate, and a doped negative charge layer is right next to the positive fixed charge layer. The present invention also provides a method of forming said silicon on insulator (SOI) device.

公开(公告)号：US20230387250A1

公开(公告)日：2023-11-30

申请号：US17842814

申请日：2022-06-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/42312 ,  H01L29/778

Abstract: An HEMT with a stair-like compound layer as a drain includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A source electrode, a gate electrode and a drain electrode are disposed on the second III-V compound layer. The gate electrode is disposed between the source electrode and the drain electrode. A first P-type III-V compound layer is disposed between the drain electrode and the second III-V compound layer. The first P-type III-V compound layer is stair-like.

公开(公告)号：US11832536B2

公开(公告)日：2023-11-28

申请号：US17834909

申请日：2022-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H10N70/00

CPC classification number: H10N70/841 ,  H10N70/021 ,  H10N70/063 ,  H10N70/826

Abstract: A resistive memory device includes a first stacked structure and a second stacked structure. The first stacked structure includes a first bottom electrode, a first top electrode disposed on the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode in a vertical direction. The second stacked structure includes a second bottom electrode, a second top electrode disposed on the second bottom electrode, and a second variable resistance layer disposed between the second bottom electrode and the second top electrode in the vertical direction. A thickness of the first variable resistance layer is less than a thickness of the second variable resistance layer for increasing the number of switchable resistance states of the resistive memory device.

公开(公告)号：US20230253489A1

公开(公告)日：2023-08-10

申请号：US18134582

申请日：2023-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/66462

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, and a gate electrode. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer, where the surface of the semiconductor barrier layer includes at least one recess. The gate electrode is disposed on the semiconductor barrier layer and includes a body portion and at least one vertical extension portion overlapping the recess.

公开(公告)号：US11721697B2

公开(公告)日：2023-08-08

申请号：US17735114

申请日：2022-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Yu-Wen Hung

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/092 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356

Abstract: A manufacturing method of a semiconductor device is provided in an embodiment of the present invention. The manufacturing method includes the following steps. A transistor is formed on a substrate. The transistor includes a plurality of semiconductor sheets and two source/drain structures. The semiconductor sheets are stacked in a vertical direction and separated from one another. Each of the semiconductor sheets includes two first doped layers and a second doped layer disposed between the two first doped layers in the vertical direction. A conductivity type of the second doped layer is complementary to a conductivity type of each of the two first doped layers. The two source/drain structures are disposed at two opposite sides of each of the semiconductor sheets in a horizontal direction respectively, and the two source/drain structures are connected with the semiconductor sheets.