公开(公告)号：US10247774B2

公开(公告)日：2019-04-02

申请号：US15369905

申请日：2016-12-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Hsien Chen ,  Sheng-Yuan Hsueh ,  Yi-Chung Sheng ,  Wen-Kai Lin ,  Chih-Kai Kang

IPC: G01R31/28 ,  H01L21/66

Abstract: The present invention provides a test key structure for measuring or simulating a target via array. The structure includes a substrate with a test region, a plurality of first conductive lines in the test region; a plurality of second conductive lines in the test region and on the first conductive lines, wherein the first conductive lines and the second conductive lines overlaps vertically in a plurality of target regions, and a plurality of vias disposed between the first conductive lines and the second conductive lines, wherein at least two vias vertically contact one of the first conductive lines and one of the second conductive lines. The present invention further provides a method of measuring resistance by using the testkey structure.

公开(公告)号：US20180269201A1

公开(公告)日：2018-09-20

申请号：US15983096

申请日：2018-05-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Hsien Chen ,  Sheng-Yuan Hsueh ,  Yi-Chung Sheng ,  Chih-Kai Kang ,  Wen-Kai Lin ,  Shu-Hung Yu

IPC: H01L27/06 ,  H01L29/06 ,  H01L23/528 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L27/0629 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5223 ,  H01L23/5283 ,  H01L28/60 ,  H01L29/0649

Abstract: A method of forming a capacitor includes the following steps. First, a substrate is provided. A dielectric layer is formed over the substrate. A first patterning process is performed to form a first contact plug through the whole thickness of the dielectric layer and a second patterning process is performed to form a second contact plug in the dielectric layer and spaced apart from the first contact plug in a pre-determined distance, wherein the first contact plug and the second contact plug are capacitively coupled.

公开(公告)号：US12200947B2

公开(公告)日：2025-01-14

申请号：US18395762

申请日：2023-12-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Hsiang Huang ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H10B61/00 ,  H10N50/10 ,  H10N50/80

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.

公开(公告)号：US20250014661A1

公开(公告)日：2025-01-09

申请号：US18890725

申请日：2024-09-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai ,  Chih-Kai Kang

IPC: G11C17/16 ,  H10B20/25

Abstract: A bit cell structure for one-time-programming is provided in the present invention, including a first doped region in a substrate and electrically connected to a source line, a second doped region in the substrate and provided with a source and a drain, wherein the drain is electrically connected with a bit line, a doped channel region in the substrate with a first part and a second part connecting respectively to the first doped region and the source of second doped region in a first direction, and a width of the first part in a second direction perpendicular to the first direction is less than a width of the second part and less than a width of the first doped region, and a word line traversing over the second doped region and between the source and drain.

公开(公告)号：US20240153812A1

公开(公告)日：2024-05-09

申请号：US18074511

申请日：2022-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Kai Lin ,  Chi-Horn Pai ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H01L21/762 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L21/762 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/66545

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a shallow trench isolation (STI) in a substrate, forming a first gate structure on the substrate and adjacent to the STI, forming a first doped region between the first gate structure and the STI, forming a second doped region between the first doped region and the first gate structure, forming a first contact plug on the first doped region, and then forming a second contact plug on the second doped region.

公开(公告)号：US11605631B2

公开(公告)日：2023-03-14

申请号：US17516721

申请日：2021-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Chen Chiu ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chien-Liang Wu ,  Chih-Kai Kang ,  Guan-Kai Huang

IPC: H01L27/085 ,  H01L27/06 ,  H01L29/66 ,  H01L29/778

Abstract: A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.

公开(公告)号：US20230071086A1

公开(公告)日：2023-03-09

申请号：US17987795

申请日：2022-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Hsiang Huang ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.

公开(公告)号：US20220328504A1

公开(公告)日：2022-10-13

申请号：US17320234

申请日：2021-05-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai ,  Chih-Kai Kang

IPC: H01L27/112 ,  G11C17/16

Abstract: A bit cell structure for one-time programming is provided in the present invention, including a substrate, a first doped region in the substrate and electrically connecting a source line, a second doped region in the substrate and having a source and a drain electrically connecting a bit line, a heavily-doped channel in the substrate and connecting the first doped region and the source of second doped region, and a word line crossing over the second dope region between the source and the drain.

公开(公告)号：US20220181478A1

公开(公告)日：2022-06-09

申请号：US17676867

申请日：2022-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang ,  Guan-Kai Huang ,  Chien-Liang Wu

IPC: H01L29/778 ,  H01L29/66

Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).

公开(公告)号：US11316031B2

公开(公告)日：2022-04-26

申请号：US16741725

申请日：2020-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L21/84

Abstract: A method of forming a fin forced stack inverter includes the following steps. A substrate including a first fin, a second fin and a third fin across a first active area along a first direction is provided, wherein the first fin, the second fin and the third fin are arranged side by side. A fin remove inside active process is performed to remove at least a part of the second fin in the first active area. A first gate is formed across the first fin and the third fin in the first active area along a second direction. The present invention also provides a 1-1 fin forced fin stack inverter formed by said method.