公开(公告)号：US09514993B2

公开(公告)日：2016-12-06

申请号：US14664933

申请日：2015-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Wei Yu ,  Ted Ming-Lang Guo ,  Hsu Ting ,  Yu-Ren Wang

IPC: H01L21/8238 ,  H01L21/283 ,  H01L21/308

CPC classification number: H01L21/823814 ,  H01L21/02236 ,  H01L21/283 ,  H01L21/3083 ,  H01L21/3085 ,  H01L21/31111 ,  H01L21/823425 ,  H01L21/823878

Abstract: A method for manufacturing semiconductor devices includes following steps. A substrate including a first gate structure and a second gate structure formed thereon is provided. The first gate structure and the second gate structure are complementary to each other. Next, a first mask layer covering the second gate structure is formed and followed by forming first recesses in the substrate at two respective sides of the first transistor. Then, forming the first recesses, a first epitaxial layer is formed in each first recess. After forming the first epitaxial layers, a local protecting cap is formed on the first epitaxial layers and followed by removing the first mask layer.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 提供了包括形成在其上的第一栅极结构和第二栅极结构的衬底。 第一栅极结构和第二栅极结构彼此互补。 接下来，形成覆盖第二栅极结构的第一掩模层，随后在第一晶体管的两个相应的两侧在衬底中形成第一凹槽。 然后，形成第一凹部，在每个第一凹部中形成第一外延层。 在形成第一外延层之后，在第一外延层上形成局部保护帽，然后除去第一掩模层。

公开(公告)号：US20160284601A1

公开(公告)日：2016-09-29

申请号：US14664933

申请日：2015-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Wei Yu ,  Ted Ming-Lang Guo ,  Hsu Ting ,  Yu-Ren Wang

IPC: H01L21/8238 ,  H01L21/308 ,  H01L21/283

CPC classification number: H01L21/823814 ,  H01L21/02236 ,  H01L21/283 ,  H01L21/3083 ,  H01L21/3085 ,  H01L21/31111 ,  H01L21/823425 ,  H01L21/823878

Abstract: A method for manufacturing semiconductor devices includes following steps. A substrate including a first gate structure and a second gate structure formed thereon is provided. The first gate structure and the second gate structure are complementary to each other. Next, a first mask layer covering the second gate structure is formed and followed by forming first recesses in the substrate at two respective sides of the first transistor. Then, forming the first recesses, a first epitaxial layer is formed in each first recess. After forming the first epitaxial layers, a local protecting cap is formed on the first epitaxial layers and followed by removing the first mask layer.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 提供了包括形成在其上的第一栅极结构和第二栅极结构的衬底。 第一栅极结构和第二栅极结构彼此互补。 接下来，形成覆盖第二栅极结构的第一掩模层，随后在第一晶体管的两个相应的两侧在衬底中形成第一凹槽。 然后，形成第一凹部，在每个第一凹部中形成第一外延层。 在形成第一外延层之后，在第一外延层上形成局部保护帽，然后除去第一掩模层。

公开(公告)号：US20250072060A1

公开(公告)日：2025-02-27

申请号：US18943871

申请日：2024-11-11

Applicant: United Microelectronics Corp.

Inventor： Kuang-Hsiu Chen ,  Wei-Chung Sun ,  Chao Nan Chen ,  Chun-Wei Yu ,  Kuan Hsuan Ku ,  Shao-Wei Wang

IPC: H01L29/66

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes the following. A gate structure is formed on a substrate. A tilt implanting process is performed to implant group IV elements into the substrate to form a doped region, and the doped region is located on two sides of the gate structure and partially located under the gate structure. A part of the substrate on two sides of the gate structure is removed to form a first recess. A cleaning process is performed on the surface of the first recess. A wet etching process is performed on the first recess to form a second recess. A semiconductor layer is formed in the second recess.

公开(公告)号：US20210280717A1

公开(公告)日：2021-09-09

申请号：US17330443

申请日：2021-05-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Sung-Yuan Tsai ,  Chi-Hsuan Tang ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.

公开(公告)号：US10796943B2

公开(公告)日：2020-10-06

申请号：US16181354

申请日：2018-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Chun-Wei Yu ,  Yu-Ren Wang ,  Shi-You Liu ,  Shao-Hua Hsu

IPC: H01L21/762 ,  H01L21/3115 ,  H01L21/308 ,  H01L21/306

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned mask layer is formed on a semiconductor substrate. An isolation trench is formed in the semiconductor substrate by removing a part of the semiconductor substrate. A liner layer is conformally formed on an inner sidewall of the isolation trench. An implantation process is performed to the liner layer. The implantation process includes a noble gas implantation process. An isolation structure is at least partially formed in the isolation trench after the implantation process. An etching process is performed to remove the patterned mask layer after forming the isolation structure and expose a top surface of the semiconductor substrate. A part of the liner layer formed on the inner sidewall of the isolation trench is removed by the etching process. The implantation process is configured to modify the etch rate of the liner layer in the etching process.

公开(公告)号：US20200144102A1

公开(公告)日：2020-05-07

申请号：US16181354

申请日：2018-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Chun-Wei Yu ,  Yu-Ren Wang ,  Shi-You Liu ,  Shao-Hua Hsu

IPC: H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3115

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned mask layer is formed on a semiconductor substrate. An isolation trench is formed in the semiconductor substrate by removing a part of the semiconductor substrate. A liner layer is conformally formed on an inner sidewall of the isolation trench. An implantation process is performed to the liner layer. The implantation process includes a noble gas implantation process. An isolation structure is at least partially formed in the isolation trench after the implantation process. An etching process is performed to remove the patterned mask layer after forming the isolation structure and expose a top surface of the semiconductor substrate. A part of the liner layer formed on the inner sidewall of the isolation trench is removed by the etching process. The implantation process is configured to modify the etch rate of the liner layer in the etching process.

公开(公告)号：US20200098916A1

公开(公告)日：2020-03-26

申请号：US16172856

申请日：2018-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Sung-Yuan Tsai ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Chao-Nan Chen ,  Shi-You Liu ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L21/265

Abstract: A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.

公开(公告)号：US10559655B1

公开(公告)日：2020-02-11

申请号：US16210738

申请日：2018-12-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Chia-Ming Kuo ,  Fu-Jung Chuang ,  Chun-Wei Yu ,  Po-Jen Chuang ,  Yu-Ren Wang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/51 ,  H01L21/768 ,  H01L29/78 ,  H01L21/764

Abstract: A semiconductor device comprises at least one gate structure disposed on a substrate; a first dielectric layer disposed on the substrate and contacting an outer sidewall of the at least one gate structure; a second dielectric layer having a L shape disposed on the first dielectric layer and contacting the outer sidewall of the at least one gate structure; an etch stop layer contacting the second dielectric layer, the first dielectric layer and the substrate, wherein the second dielectric layer has an upper portion and a lower portion contacting the upper portion, the upper portion extends along the outer sidewall, the lower portion extends from the outer sidewall to the etch stop layer; and an air gap between the second dielectric layer and the etch stop layer; wherein the first dielectric layer and the lower portion of the second dielectric layer have a same width.

公开(公告)号：US10340268B2

公开(公告)日：2019-07-02

申请号：US15284552

申请日：2016-10-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L29/51 ,  H01L27/088 ,  H01L21/8234

Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.

公开(公告)号：US20190006172A1

公开(公告)日：2019-01-03

申请号：US15639381

申请日：2017-06-30

Applicant: United Microelectronics Corp.

Inventor： Hsu Ting ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Keng-Jen Lin ,  Yu-Ren Wang

IPC: H01L21/02

Abstract: A method for processing a semiconductor device is provided. The semiconductor device includes a protruding structure on a substrate, the protruding structure having a nitride spacer at a sidewall, and an epitaxial layer is formed in the substrate adjacent to the protruding structure. The method includes removing the nitride spacer on the protruding structure. Then, a dilute hydrofluoric (DHF) cleaning process is performed over the substrate, wherein a top surficial portion of the epitaxial layer is removed. A standard clean (SC) process is performed over the substrate, wherein a native oxide layer is formed on an expose surface of the epitaxial layer.