公开(公告)号：US20190157455A1

公开(公告)日：2019-05-23

申请号：US15820443

申请日：2017-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Hsu Ting ,  Chung-Fu Chang ,  Shi-You Liu ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L21/3105 ,  H01L21/02532 ,  H01L21/26533 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating a semiconductor device. A gate is formed on a substrate. A spacer is formed on each sidewall of the gate. A hard mask layer is formed on the spacer. A recessed region is formed in the substrate and adjacent to the hard mask layer. An epitaxial layer is formed in the recessed region. The substrate is subjected to an ion implantation process to bombard particle defects on the hard mask layer with inert gas ions. An annealing process is performed to repair damages to the epitaxial layer caused by the ion implantation process. The hard mask layer is then removed.

公开(公告)号：US20170330742A1

公开(公告)日：2017-11-16

申请号：US15636660

申请日：2017-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L21/0206 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes fin shaped structures and a recessed insulating layer. The fin shaped structures are disposed on a substrate. The recessed insulating layer covers a bottom portion of each of the fin shaped structures to expose a top portion of each of the fin shaped structures. The recessed insulating layer has a curve surface and a wicking structure is defined between a peak and a bottom of the curve surface. The wicking structure is disposed between the fin shaped structures and has a height being about 1/12 to 1/10 of a height of the top portion of the fin shaped structures.

公开(公告)号：US20220365433A1

公开(公告)日：2022-11-17

申请号：US17316736

申请日：2021-05-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Hsuan Chang ,  Da-Jun Lin ,  Yao-Hsien Chung ,  Ting-An Chien ,  Bin-Siang Tsai ,  Chih-Wei Chang ,  Shih-Wei Su ,  Hsu Ting ,  Sung-Yuan Tsai

IPC: G03F7/075 ,  G03F7/20

Abstract: A fabricating method of reducing photoresist footing includes providing a silicon nitride layer. Later, a fluorination process is performed to graft fluoride ions onto a top surface of the silicon nitride layer. After the fluorination process, a photoresist is formed to contact the top surface of the silicon nitride layer. Finally, the photoresist is patterned to remove at least part of the photoresist contacting the silicon nitride layer.

公开(公告)号：US10460925B2

公开(公告)日：2019-10-29

申请号：US15639381

申请日：2017-06-30

Applicant: United Microelectronics Corp.

Inventor： Hsu Ting ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Keng-Jen Lin ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L21/311 ,  H01L29/66

Abstract: A method for processing a semiconductor device is provided. The semiconductor device includes a protruding structure on a substrate, the protruding structure having a nitride spacer at a sidewall, and an epitaxial layer is formed in the substrate adjacent to the protruding structure. The method includes removing the nitride spacer on the protruding structure. Then, a dilute hydrofluoric (DHF) cleaning process is performed over the substrate, wherein a top surficial portion of the epitaxial layer is removed. A standard clean (SC) process is performed over the substrate, wherein a native oxide layer is formed on an expose surface of the epitaxial layer.

公开(公告)号：US10366991B1

公开(公告)日：2019-07-30

申请号：US15880492

申请日：2018-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Yu-Ying Lin ,  Yen-Hsing Chen ,  Chun-Jen Chen ,  Chun-Wei Yu ,  Keng-Jen Lin ,  Yu-Ren Wang

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes fin shaped structures. The isolation structure is disposed between the fin shaped structures. Each of the fin shaped structures includes a first portion disposed above a top surface of the isolation structure and a second portion disposed on the first portion. A width of the second portion is smaller than a width of the first portion. The cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures. The cladding layer includes a curved surface. The gate structure is disposed straddling the fin shaped structures.

公开(公告)号：US11762293B2

公开(公告)日：2023-09-19

申请号：US17316736

申请日：2021-05-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Hsuan Chang ,  Da-Jun Lin ,  Yao-Hsien Chung ,  Ting-An Chien ,  Bin-Siang Tsai ,  Chih-Wei Chang ,  Shih-Wei Su ,  Hsu Ting ,  Sung-Yuan Tsai

IPC: G03F7/075 ,  G03F7/20 ,  C23C16/34

CPC classification number: G03F7/0755 ,  G03F7/2043 ,  C23C16/345

Abstract: A fabricating method of reducing photoresist footing includes providing a silicon nitride layer. Later, a fluorination process is performed to graft fluoride ions onto a top surface of the silicon nitride layer. After the fluorination process, a photoresist is formed to contact the top surface of the silicon nitride layer. Finally, the photoresist is patterned to remove at least part of the photoresist contacting the silicon nitride layer.

公开(公告)号：US10332750B2

公开(公告)日：2019-06-25

申请号：US15820443

申请日：2017-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Hsu Ting ,  Chung-Fu Chang ,  Shi-You Liu ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L21/3105 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L29/165 ,  H01L21/266 ,  H01L21/324 ,  H01L29/08

Abstract: A method for fabricating a semiconductor device. A gate is formed on a substrate. A spacer is formed on each sidewall of the gate. A hard mask layer is formed on the spacer. A recessed region is formed in the substrate and adjacent to the hard mask layer. An epitaxial layer is formed in the recessed region. The substrate is subjected to an ion implantation process to bombard particle defects on the hard mask layer with inert gas ions. An annealing process is performed to repair damages to the epitaxial layer caused by the ion implantation process. The hard mask layer is then removed.

公开(公告)号：US10079143B2

公开(公告)日：2018-09-18

申请号：US15636660

申请日：2017-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L21/0206 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0657

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes fin shaped structures and a recessed insulating layer. The fin shaped structures are disposed on a substrate. The recessed insulating layer covers a bottom portion of each of the fin shaped structures to expose a top portion of each of the fin shaped structures. The recessed insulating layer has a curve surface and a wicking structure is defined between a peak and a bottom of the curve surface. The wicking structure is disposed between the fin shaped structures and has a height being about 1/12 to 1/10 of a height of the top portion of the fin shaped structures.

公开(公告)号：US09728397B1

公开(公告)日：2017-08-08

申请号：US15150444

申请日：2016-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L21/02 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L21/0206 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes fin shaped structures and a recessed insulating layer. The fin shaped structures are disposed on a substrate. The recessed insulating layer covers a bottom portion of each of the fin shaped structures to expose a top portion of each of the fin shaped structures. The recessed insulating layer has a curve surface and a wicking structure is defined between a peak and a bottom of the curve surface. The wicking structure is disposed between the fin shaped structures and has a height being about 1/12 to 1/10 of a height of the top portion of the fin shaped structures.

公开(公告)号：US20170200824A1

公开(公告)日：2017-07-13

申请号：US15469569

申请日：2017-03-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Wei Yu ,  Hsu Ting ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Kuang-Hsiu Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/45 ,  H01L29/417

CPC classification number: H01L29/7845 ,  H01L21/02065 ,  H01L21/28123 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device includes: a substrate; a gate structure on the substrate; and an epitaxial layer in the substrate adjacent to the gate structure, in which the epitaxial layer includes a planar surface and protrusions adjacent to two sides of the planar surface. Preferably, a contact plug is embedded in part of the epitaxial layer, and a silicide is disposed under the contact plug, in which a bottom surface of the silicide includes an arc.