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公开(公告)号：US20230380296A1
公开(公告)日：2023-11-23
申请号：US18230189
申请日：2023-08-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chiu-Jung Chiu , Ya-Sheng Feng , I-Ming Tseng , Yi-An Shih , Yu-Chun Chen , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
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公开(公告)号：US11765983B2
公开(公告)日：2023-09-19
申请号：US17972542
申请日：2022-10-24
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chiu-Jung Chiu , Ya-Sheng Feng , I-Ming Tseng , Yi-An Shih , Yu-Chun Chen , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
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公开(公告)号：US20230040932A1
公开(公告)日：2023-02-09
申请号：US17972542
申请日：2022-10-24
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chiu-Jung Chiu , Ya-Sheng Feng , I-Ming Tseng , Yi-An Shih , Yu-Chun Chen , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
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公开(公告)号：US11552001B2
公开(公告)日：2023-01-10
申请号：US17121696
申请日：2020-12-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chung-Liang Chu , Yu-Ruei Chen
IPC: H01L23/48 , H01L29/78 , H01L21/8234 , H01L21/8238
Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a second gate structure, a first slot contact structure, a first gate contact structure, and a second gate contact structure. The substrate includes a first active region and a second active region elongated in a first direction respectively. The first gate structure, the second gate structure, and the first slot contact structure are continuously elongated in a second direction respectively. The first gate contact structure and the second gate contact structure are disposed at two opposite sides of the first slot contact structure in the first direction respectively.
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公开(公告)号：US11515471B2
公开(公告)日：2022-11-29
申请号：US16988707
申请日：2020-08-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chiu-Jung Chiu , Ya-Sheng Feng , I-Ming Tseng , Yi-An Shih , Yu-Chun Chen , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
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Patent Agency Ranking
公开(公告)号：US20210184104A1
公开(公告)日：2021-06-17
申请号：US17182146
申请日：2021-02-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chung-Liang Chu , Jian-Cheng Chen , Yu-Ping Wang , Yu-Ruei Chen
Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.
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公开(公告)号：US10930839B2
公开(公告)日：2021-02-23
申请号：US16739060
申请日：2020-01-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chung-Liang Chu , Jian-Cheng Chen , Yu-Ping Wang , Yu-Ruei Chen
Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region comprises an octagon and the ring of MTJ region includes a first MTJ region and a second MTJ region extending along a first direction, a third MTJ region and a fourth MTJ region extending along a second direction, a fifth MTJ region and a sixth MTJ region extending along a third direction, and a seventh MTJ region and an eighth MTJ region extending along a fourth direction.
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公开(公告)号：US20190074272A1
公开(公告)日：2019-03-07
申请号：US16175867
申请日：2018-10-31
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chung-Liang Chu , Yu-Ruei Chen , Yu-Hsiang Lin
IPC: H01L27/02 , H01L21/8234 , H01L27/088
Abstract: A dummy cell arrangement in a semiconductor device includes a substrate with a dummy region, unit dummy cells arranged in rows and columns in the dummy region, and flexible extended dummy cells arranged in rows and columns filling up remaining dummy region. The unit dummy cell includes exactly one base dummy cell and exactly two fixed dummy cells at opposite sides of the base dummy cell in row direction or in column direction and the flexible extended dummy cell includes at least two base dummy units and a plurality of flexible dummy units at two opposite sides of the two base dummy units in row direction or in column direction. The base dummy cell consists of at least one fin, at least one gate and at least one contact, while the flexible dummy cell consists of one gate and one contact without any fin.
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公开(公告)号：US11721702B2
公开(公告)日：2023-08-08
申请号：US17844067
申请日：2022-06-20
Applicant: United Microelectronics Corp.
Inventor： Sheng-Yao Huang , Yu-Ruei Chen , Chung-Liang Chu , Zen-Jay Tsai , Yu-Hsiang Lin
IPC: H01L27/12 , H01L21/8234 , H01L29/66 , H01L29/78
CPC classification number: H01L27/1211 , H01L21/823431 , H01L29/66795 , H01L29/785
Abstract: A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.
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公开(公告)号：US11611035B2
公开(公告)日：2023-03-21
申请号：US17182146
申请日：2021-02-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chung-Liang Chu , Jian-Cheng Chen , Yu-Ping Wang , Yu-Ruei Chen
Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.
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