公开(公告)号：US20240266435A1

公开(公告)日：2024-08-08

申请号：US18120980

申请日：2023-03-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Tsai ,  Chin-Chia Kuo ,  Wei-Hsuan Chang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7835 ,  H01L29/6659

Abstract: A transistor with an embedded insulating structure set includes a substrate. A gate is disposed on the substrate. A first lightly doped region is disposed at one side of the gate. A second lightly doped region is disposed at another side of the gate. The first lightly doped region and the second lightly doped region have the same conductive type. The first lightly doped region is symmetrical to the second lightly doped region. A first source/drain doped region is disposed within the first lightly doped region. A second source/drain doped region is disposed within the second lightly doped region. A first insulating structure set is disposed within the first lightly doped region and the first source/drain doped region. The first insulating structure set includes an insulating block embedded within the substrate. A sidewall of the insulating block contacts the gate dielectric layer.

公开(公告)号：US12057483B2

公开(公告)日：2024-08-06

申请号：US18078057

申请日：2022-12-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Tsai ,  Jung Han ,  Ming-Chi Li ,  Chih-Mou Lin ,  Yu-Hsiang Hung ,  Yu-Hsiang Lin ,  Tzu-Lang Shih

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42368 ,  H01L29/0607 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

公开(公告)号：US20240038684A1

公开(公告)日：2024-02-01

申请号：US17889389

申请日：2022-08-16

Applicant: United Microelectronics Corp.

Inventor： Ming-Hua Tsai ,  Hao Ping Yan ,  Chin-Chia Kuo ,  Wei Hsuan Chang

IPC: H01L23/00 ,  H01L23/544 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L23/544 ,  H01L23/564 ,  H01L23/585 ,  H01L2223/5446 ,  H01L2223/54426

Abstract: A semiconductor structure including a substrate and protection structures is provided. The substrate includes a die region. The die region includes corner regions. The protection structures are located in the corner region. Each of the protection structures has a square top-view pattern. The square top-view patterns located in the same corner region have various sizes.

公开(公告)号：US20230335609A1

公开(公告)日：2023-10-19

申请号：US17736071

申请日：2022-05-03

Applicant: United Microelectronics Corp.

Inventor： Ming-Hua Tsai ,  Wei Hsuan Chang ,  Chin-Chia Kuo

IPC: H01L29/423 ,  H01L29/40 ,  H01L21/8234

CPC classification number: H01L29/42368 ,  H01L29/401 ,  H01L21/823462 ,  H01L27/088

Abstract: The invention provides a transistor structure and a manufacturing method thereof. The transistor structure includes a substrate, a first gate, a second gate, a first gate dielectric layer, and a second gate dielectric layer. The first gate and the second gate are located on the substrate. The first gate dielectric layer is located between the first gate and the substrate. The first gate dielectric layer has a single thickness. The second gate dielectric layer is located between the second gate and the substrate. The second gate dielectric layer has a plurality of thicknesses. A maximum thickness of the first gate dielectric layer is the same as a maximum thickness of the second gate dielectric layer. The transistor structure may reduce process complexity.

公开(公告)号：US20230207647A1

公开(公告)日：2023-06-29

申请号：US18115780

申请日：2023-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Tsai ,  Jung Han ,  Ming-Chi Li ,  Chih-Mou Lin ,  Yu-Hsiang Hung ,  Yu-Hsiang Lin ,  Tzu-Lang Shih

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/42368 ,  H01L29/0607 ,  H01L29/66545 ,  H01L29/0847 ,  H01L29/6659 ,  H01L29/6656 ,  H01L29/7833

Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

公开(公告)号：US20220376071A1

公开(公告)日：2022-11-24

申请号：US17369985

申请日：2021-07-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Tsai ,  Jung Han ,  Ming-Chi Li ,  Chih-Mou Lin ,  Yu-Hsiang Hung ,  Yu-Hsiang Lin ,  Tzu-Lang Shih

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

公开(公告)号：US11114390B2

公开(公告)日：2021-09-07

申请号：US16737928

申请日：2020-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsuan Chang ,  Ming-Hua Tsai ,  Chin-Chia Kuo

IPC: H01L23/522 ,  H01L27/06 ,  H01L23/00 ,  H01L49/02 ,  H01L21/762 ,  H01L27/08 ,  H01L21/3105

Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device.