公开(公告)号：US20190311901A1

公开(公告)日：2019-10-10

申请号：US15969788

申请日：2018-05-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Gang-Yi Lin ,  Feng-Yi Chang ,  Ying-Chih Lin ,  Fu-Che Lee

IPC: H01L21/033 ,  H01L21/311

Abstract: The present invention provides a method of forming a semiconductor structure including the following steps. Firstly, a target layer is formed on a substrate, and a plurality of mandrels is formed on the target layer. Next, a material layer is formed on the target layer to cover the mandrels. Then, an etching process is performed to partially remove each of the mandrel and the material layer covered on each mandrel, to form a plurality of mask. Finally, the target layer is patterned through the masks, to form a plurality of patterns. Through the present invention, each mask comprises an unetched portion of each mandrel and a spacer portion of the material covered on each mandrel, and a dimension of each of the patterns is larger than a dimension of each of the mandrel.

公开(公告)号：US10354876B1

公开(公告)日：2019-07-16

申请号：US16016647

申请日：2018-06-24

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Yu-Cheng Tung ,  Fu-Che Lee ,  Ying-Chih Lin

IPC: H01L21/033 ,  H01L27/108

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate and a material layer. The substrate has a first region, and the material layer is disposed on the substrate. The material layer includes plural of first patterns and plural of second patterns arranged in an array, and two third patterns. The first patterns are disposed within the first region, the second patterns are disposed at two opposite outer sides of the first region, and the third patterns are disposed at another two opposite outer sides of the first region, wherein each of the third patterns partially merges each of a part of the first patterns and each of a part of the second patterns.

公开(公告)号：US10312088B1

公开(公告)日：2019-06-04

申请号：US15900764

申请日：2018-02-20

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Ying-Chih Lin ,  Gang-Yi Lin

IPC: H01L21/033 ,  H01L27/108

Abstract: A self-aligned double patterning method includes the steps of forming line structures spaced apart from each other in a first direction on a mask layer, forming dielectric layer on the line structures, performing an etch back process so that the top surfaces of the line structures and the dielectric layer are flush, forming layer structure with same material as the line structures on the line structures and the dielectric layer, forming spacers spaced apart from each other in a second direction on the layer structure, and performing an etch process with the spacers as an etch mask to pattern the line structures and the dielectric layer.

公开(公告)号：US20190139824A1

公开(公告)日：2019-05-09

申请号：US16134976

申请日：2018-09-19

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Ying-Chih Lin ,  Gang-Yi Lin ,  Chieh-Te Chen ,  Yi-Ching Chang

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/28 ,  H01L21/308

Abstract: A method of self-aligned double patterning is disclosed in the present invention, which includes the step of forming multiple mandrels on a hard mask layer and spacers at two sides of each mandrel, forming a protection layer filling between the spacers, removing the mandrels to expose the hard mask layer, and performing an anisotropic etch process using the spacers and the protection layer as an etch mask to remove a portion of hard mask layer, so that a thickness of hard mask layer exposed between the spacers equals to a thickness of hard mask layer under the protection layer.

公开(公告)号：US09013024B2

公开(公告)日：2015-04-21

申请号：US14054811

申请日：2013-10-15

Applicant: United Microelectronics Corp.

Inventor： Ying-Chih Lin ,  Hsuan-Hsu Chen ,  Jiunn-Hsiung Liao ,  Lung-En Kuo

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/308 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L21/311 ,  H01L21/3083 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.

Abstract translation: 半导体结构包括基板，凹部和材料。 凹部位于基板中，其中凹部具有上部和下部。 上部的最小宽度大于下部的最大宽度。 材料位于凹槽中。

公开(公告)号：US20140038417A1

公开(公告)日：2014-02-06

申请号：US14054811

申请日：2013-10-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ying-Chih Lin ,  Hsuan-Hsu Chen ,  Jiunn-Hsiung Liao ,  Lung-En Kuo

IPC: H01L21/311

CPC classification number: H01L21/311 ,  H01L21/3083 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.

Abstract translation: 半导体结构包括基板，凹部和材料。 凹部位于基板中，其中凹部具有上部和下部。 上部的最小宽度大于下部的最大宽度。 材料位于凹槽中。