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公开(公告)号：US11545547B2
公开(公告)日：2023-01-03
申请号：US17317912
申请日：2021-05-12
Inventor： Feng-Yi Chang , Fu-Che Lee , Yi-Ching Chang , Kai-Lou Huang , Ying-Chih Lin , Gang-Yi Lin
IPC: H01L29/76 , H01L29/06 , H01L21/027 , H01L29/66 , H01L21/3213 , H01L21/033 , H01L21/311
Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.
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公开(公告)号：US20210265462A1
公开(公告)日：2021-08-26
申请号：US17317912
申请日：2021-05-12
Inventor： Feng-Yi Chang , Fu-Che Lee , Yi-Ching Chang , Kai-Lou Huang , Ying-Chih Lin , Gang-Yi Lin
IPC: H01L29/06 , H01L21/027 , H01L29/66 , H01L21/3213 , H01L21/033 , H01L21/311
Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.
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公开(公告)号：US20190385847A1
公开(公告)日：2019-12-19
申请号：US16024907
申请日：2018-07-01
Inventor： Feng-Yi Chang , Fu-Che Lee , Ying-Chih Lin , Gang-Yi Lin
IPC: H01L21/033 , H01L21/027 , H01L21/311 , H01L27/108
Abstract: A method of forming a capacitor mask includes the following steps. A bulk mandrel and a plurality of strip mandrels are formed on a mask layer. Spacers are formed on sidewalls of the bulk mandrel and the strip mandrels. The strip mandrels are removed while the bulk mandrel is reserved. A material fills in space between the spacers and on the bulk mandrel, wherein the material has a flat top surface. A patterned photoresist is formed to cover the bulk mandrel and a part of the spacers but exposing the other part of the spacers after filling the material.
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公开(公告)号：US20190181014A1
公开(公告)日：2019-06-13
申请号：US16167435
申请日：2018-10-22
Inventor： Feng-Yi Chang , Fu-Che Lee , Ying-Chih Lin , Gang-Yi Lin
IPC: H01L21/308 , H01L21/8234 , H01L21/033
Abstract: A patterning method for forming a semiconductor device is disclosed. A substrate having a hard mask disposed thereon is provided. A first patterned layer is formed on the hard mask layer. A first self-aligned double patterning process based on the first patterned layer is performed to pattern the hard mask layer into a first array pattern and a first peripheral pattern. After that, a second patterned layer is formed on the substrate. A second self-aligned double patterning process based on the second patterned layer is performed to pattern the first array pattern into a second array pattern. Subsequently, a third patterned layer is formed on the substrate. An etching process using the third patterned mask layer as an etching mask is performed to etch the first peripheral pattern thereby patterning the first peripheral pattern into a second peripheral pattern.
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公开(公告)号：US20150004766A1
公开(公告)日：2015-01-01
申请号：US14487103
申请日：2014-09-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Shih-Hung Tsai , Ssu-I Fu , Ying-Tsung Chen , Chih-Wei Chen , Ying-Chih Lin , Chien-Ting Lin , Hsuan-Hsu Chen
CPC classification number: H01L29/66795 , H01L29/51 , H01L29/66818 , H01L29/785
Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.
Abstract translation: 本发明提供一种非平面FET，其包括基板，鳍结构，子间隔物，栅极，电介质层和源极/漏极区域。 翅片结构设置在基板上。 子间隔件仅设置在翅片结构的中间侧壁上。 门设置在翅片结构上。 介电层设置在翅片结构和栅极之间。 源/漏区设置在鳍结构中。 本发明还提供一种形成该方法的方法。
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Patent Agency Ranking
公开(公告)号：US11038014B2
公开(公告)日：2021-06-15
申请号：US16154704
申请日：2018-10-08
Inventor： Feng-Yi Chang , Fu-Che Lee , Yi-Ching Chang , Kai-Lou Huang , Ying-Chih Lin , Gang-Yi Lin
IPC: H01L29/76 , H01L29/06 , H01L21/027 , H01L29/66 , H01L21/3213 , H01L21/033 , H01L21/311
Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.
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公开(公告)号：US10672612B2
公开(公告)日：2020-06-02
申请号：US15969788
申请日：2018-05-03
Inventor： Gang-Yi Lin , Feng-Yi Chang , Ying-Chih Lin , Fu-Che Lee
IPC: H01L21/033 , H01L21/311
Abstract: The present invention provides a method of forming a semiconductor structure including the following steps. Firstly, a target layer is formed on a substrate, and a plurality of mandrels is formed on the target layer. Next, a material layer is formed on the target layer to cover the mandrels. Then, an etching process is performed to partially remove each of the mandrel and the material layer covered on each mandrel, to form a plurality of mask. Finally, the target layer is patterned through the masks, to form a plurality of patterns. Through the present invention, each mask comprises an unetched portion of each mandrel and a spacer portion of the material covered on each mandrel, and a dimension of each of the patterns is larger than a dimension of each of the mandrel.
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公开(公告)号：US10192825B1
公开(公告)日：2019-01-29
申请号：US15823714
申请日：2017-11-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wei-Hao Huang , Chun-Lung Chen , Kun-Yuan Liao , Ying-Chih Lin , Chia-Lin Lu
IPC: H01L23/528 , H01L27/088
Abstract: A semiconductor device includes a first gate line, a second gate line and a first bar-shaped contact structure. The first gate line has a first long axis extending along a first direction. The second gate line is parallel to the first gate line. The first bar-shaped contact structure has a second axis forming an angle substantially greater than 0° and less than 90° with the first long axis.
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公开(公告)号：US09312365B2
公开(公告)日：2016-04-12
申请号：US14487103
申请日：2014-09-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Shih-Hung Tsai , Ssu-I Fu , Ying-Tsung Chen , Chih-Wei Chen , Ying-Chih Lin , Chien-Ting Lin , Hsuan-Hsu Chen
IPC: H01L21/336 , H01L29/66 , H01L29/78 , H01L29/51
CPC classification number: H01L29/66795 , H01L29/51 , H01L29/66818 , H01L29/785
Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.
Abstract translation: 本发明提供一种非平面FET，其包括基板，鳍结构，子间隔物，栅极，电介质层和源极/漏极区域。 翅片结构设置在基板上。 子间隔件仅设置在翅片结构的中间侧壁上。 门设置在翅片结构上。 介电层设置在翅片结构和栅极之间。 源/漏区设置在鳍结构中。 本发明还提供一种形成该方法的方法。
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公开(公告)号：US10795255B2
公开(公告)日：2020-10-06
申请号：US16175858
申请日：2018-10-31
Inventor： Wei-Lun Hsu , Gang-Yi Lin , Yu-Hsiang Hung , Ying-Chih Lin , Feng-Yi Chang , Ming-Te Wei , Shih-Fang Tzou , Fu-Che Lee , Chia-Liang Liao
IPC: G03F1/36 , H01L23/538 , G03F1/38 , H01L21/033 , H01L21/308 , G03F1/00 , G03F7/20 , G03F7/00 , H01L27/108
Abstract: A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.
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