公开(公告)号：US09755902B2

公开(公告)日：2017-09-05

申请号：US14474623

申请日：2014-09-02

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Wen-Chi Chen ,  Rodney E. Hooker

IPC: H04L12/24 ,  G06F15/177

CPC classification number: H04L41/0833 ,  G06F15/177 ,  H04L41/0806

Abstract: A server includes a first module that receives information from a plurality of systems. Each system of the plurality of systems includes functional units that are dynamically configurable during operation of the system. The information from each system of the plurality of systems includes performance data collected while executing a program when the functional units are configured according to a configuration setting respective to the system. The server also includes a second module that analyzes the received information to select a best-performing configuration setting of the configuration settings received from the plurality of systems. The server also includes a third module that provides a new configuration setting to the plurality of systems. The new configuration setting is a modification of the best-performing configuration. The server iterates on receiving the information from the plurality of systems, analyzing the received information and providing the new configuration setting to the plurality of systems.

公开(公告)号：US09569363B2

公开(公告)日：2017-02-14

申请号：US14790467

申请日：2015-07-02

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  Colin Eddy

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0862 ,  G06F12/10 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/251 ,  G06F2212/6022 ,  G06F2212/6028 ,  G06F2212/684 ,  G06F2212/654

Abstract: A microprocessor includes a translation lookaside buffer and a first request to load into the microprocessor a page table entry in response to a miss of a virtual address in the translation lookaside buffer. The requested page table entry is included in a page table. The page table encompasses a plurality of cache lines including a first cache line that includes the requested page table entry. The microprocessor also includes hardware logic that makes a determination whether a second cache line physically sequential to the first cache line is outside the page table, and a second request to prefetch the second cache line into the microprocessor. The second request is selectively generated based at least on the determination made by the hardware logic.

Abstract translation: 微处理器包括翻译后备缓冲器和响应于翻译后备缓冲器中的虚拟地址的缺失而将微处理器加载到页表条目的第一请求。 请求的页表项包含在页表中。 该页表包含多条高速缓存行，包括包含所请求的页表项的第一高速缓存行。 微处理器还包括硬件逻辑，其确定与第一高速缓存行物理连续的第二高速缓存线是否在页表之外，以及将第二高速缓存线预取到微处理器中的第二请求。 至少基于硬件逻辑的判定来选择性地生成第二请求。

公开(公告)号：US09483263B2

公开(公告)日：2016-11-01

申请号：US14072428

申请日：2013-11-05

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  John D. Bunda ,  Brent Bean

IPC: G06F9/00 ,  G06F9/44 ,  G06F9/26 ,  G06F9/30

CPC classification number: G06F9/26 ,  G06F9/30145 ,  G06F9/30174

Abstract: A microprocessor includes a plurality of processing cores each comprises a corresponding memory physically located inside the core and readable by the core but not readable by the other cores (“core memory”). The microprocessor also includes a memory physically located outside all of the cores and readable by all of the cores (“uncore memory”). For each core, the uncore memory and corresponding core memory collectively provide M words of storage for microcode instructions fetchable by the core as follows: the uncore memory provides J of the M words of microcode instruction storage, and the corresponding core memory provides K of the M words of microcode instruction storage. J, K and M are counting numbers, and M=J+K. The memories are non-architecturally-visible and accessed using a fetch address provided by a non-architectural program counter, and the microcode instructions are non-architectural instructions that implement architectural instructions.

Abstract translation: 微处理器包括多个处理核心，每个处理核心包括物理上位于核心内并由核心读取但不能被其他核心（“核心存储器”）读取的对应存储器。 微处理器还包括物理上位于所有核心外的所有核心（“非存储器”）可读取的存储器。 对于每个核心，非核存储器和对应的核心存储器共同提供M个字节的存储器，用于由核心获取的微代码指令，如下：非存储器提供微代码指令存储器的M个字节的J，并且相应的核心存储器提供K M码的微码指令存储。 J，K和M是计数数，M = J + K。 存储器是非架构可见的，并且使用由非架构程序计数器提供的提取地址来访问，并且微代码指令是实施架构指令的非架构指令。

公开(公告)号：US09389863B2

公开(公告)日：2016-07-12

申请号：US14522512

申请日：2014-10-23

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

IPC: G06F9/30 ,  G06F11/07

CPC classification number: G06F9/30145 ,  G06F9/30014 ,  G06F9/30076 ,  G06F9/30185 ,  G06F9/30189 ,  G06F11/0721 ,  G06F11/0793

Abstract: A processor includes a decoder that decodes an instruction that instructs the processor to perform subsequent computations in an approximate manner and a functional unit that performs the subsequent computations in the approximate manner in response to the instruction. An instruction instructs the processor to clear an error amount associated with a value stored in a general purpose register of the processor. The error amount indicates an amount of error associated with a result of a computation performed by the processor in an approximate manner. The processor also clears the error amount in response to the instruction. Another instruction specifies a computation to be performed and includes a prefix that indicates the processor is to perform the computation in an approximate manner. The functional unit performs the computation specified by the instruction in the approximate manner specified by the prefix.

Abstract translation: 一种处理器包括一个译码器，该解码器解码指示处理器以近似方式执行后续计算的指令，以及响应该指令以近似方式执行后续计算的功能单元。 指令指示处理器清除与存储在处理器的通用寄存器中的值相关联的错误量。 错误量表示与处理器以近似的方式执行的计算结果相关联的错误量。 处理器还会根据指令清除错误量。 另一个指令指定要执行的计算，并且包括指示处理器以近似的方式执行计算的前缀。 功能单元以由前缀指定的近似方式执行由指令指定的计算。

公开(公告)号：US09251083B2

公开(公告)日：2016-02-02

申请号：US13792428

申请日：2013-03-11

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  John Michael Greer

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/6026

Abstract: A microprocessor includes a first and second hardware data prefetchers configured to prefetch data into the microprocessor according to first and second respective algorithms, which are different. The second prefetcher is configured to detect a memory access pattern within a memory region and responsively prefetch data from the memory region according the second algorithm. The second prefetcher is further configured to provide to the first prefetcher a descriptor of the memory region. The first prefetcher is configured to stop prefetching data from the memory region in response to receiving the descriptor of the memory region from the second prefetcher. The second prefetcher also provides to the first prefetcher a communication to resume prefetching data from the memory region, such as when the second prefetcher subsequently detects that a predetermined number of memory accesses to the memory region are not in the memory access pattern.

Abstract translation: 微处理器包括第一和第二硬件数据预取器，其被配置为根据不同的第一和第二相应算法将数据预取入微处理器。 第二预取器被配置为检测存储器区域内的存储器访问模式，并且根据第二算法响应地从存储器区域预取数据。 第二预取器还被配置为向第一预取器提供存储器区域的描述符。 响应于从第二预取器接收到存储器区域的描述符，第一预取器被配置为停止从存储器区域预取数据。 第二预取器还向第一预取器提供通信以恢复从存储器区域预取数据，例如当第二预取器随后检测到对存储器区域的预定数量的存储器访问不在存储器访问模式中时。

公开(公告)号：US20140297993A1

公开(公告)日：2014-10-02

申请号：US14072428

申请日：2013-11-05

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  John D. Bunda ,  Brent Bean

IPC: G06F9/30

CPC classification number: G06F9/26 ,  G06F9/30145 ,  G06F9/30174

Abstract: A microprocessor includes a plurality of processing cores each comprises a corresponding memory physically located inside the core and readable by the core but not readable by the other cores (“core memory”). The microprocessor also includes a memory physically located outside all of the cores and readable by all of the cores (“uncore memory”). For each core, the uncore memory and corresponding core memory collectively provide M words of storage for microcode instructions fetchable by the core as follows: the uncore memory provides J of the M words of microcode instruction storage, and the corresponding core memory provides K of the M words of microcode instruction storage. J, K and M are counting numbers, and M=J+K. The memories are non-architecturally-visible and accessed using a fetch address provided by a non-architectural program counter, and the microcode instructions are non-architectural instructions that implement architectural instructions.

Abstract translation: 微处理器包括多个处理核心，每个处理核心包括物理上位于核心内并由核心读取但不能被其他核心（“核心存储器”）读取的对应存储器。 微处理器还包括物理上位于所有核心外的所有核心（“非存储器”）可读取的存储器。 对于每个核心，非核存储器和对应的核心存储器共同提供M个字节的存储器，用于由核心获取的微代码指令，如下：非存储器提供微代码指令存储器的M个字节的J，并且相应的核心存储器提供K M码的微码指令存储。 J，K和M是计数数，M = J + K。 存储器是非架构可见的，并且使用由非架构程序计数器提供的提取地址来访问，并且微代码指令是实施架构指令的非架构指令。

公开(公告)号：US20140258641A1

公开(公告)日：2014-09-11

申请号：US13792428

申请日：2013-03-11

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  John Michael Greer

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/6026

Abstract: A microprocessor includes a first and second hardware data prefetchers configured to prefetch data into the microprocessor according to first and second respective algorithms, which are different. The second prefetcher is configured to detect a memory access pattern within a memory region and responsively prefetch data from the memory region according the second algorithm. The second prefetcher is further configured to provide to the first prefetcher a descriptor of the memory region. The first prefetcher is configured to stop prefetching data from the memory region in response to receiving the descriptor of the memory region from the second prefetcher. The second prefetcher also provides to the first prefetcher a communication to resume prefetching data from the memory region, such as when the second prefetcher subsequently detects that a predetermined number of memory accesses to the memory region are not in the memory access pattern.

Abstract translation: 微处理器包括第一和第二硬件数据预取器，其被配置为根据不同的第一和第二相应算法将数据预取入微处理器。 第二预取器被配置为检测存储器区域内的存储器访问模式，并且根据第二算法响应地从存储器区域预取数据。 第二预取器还被配置为向第一预取器提供存储器区域的描述符。 响应于从第二预取器接收到存储器区域的描述符，第一预取器被配置为停止从存储器区域预取数据。 第二预取器还向第一预取器提供通信以恢复从存储器区域预取数据，例如当第二预取器随后检测到对存储器区域的预定数量的存储器访问不在存储器访问模式中时。