公开(公告)号：US10514920B2

公开(公告)日：2019-12-24

申请号：US14625124

申请日：2015-02-18

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  Albert J. Loper ,  John Michael Greer

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0842 ,  G06F12/0831 ,  G06F3/06 ,  G06F12/0862 ,  G06F12/084

Abstract: A processor includes a processing core that detects a predetermined program is running on the processor and looks up a prefetch trait associated with the predetermined program running on the processor, wherein the prefetch trait is either exclusive or shared. The processor also includes a hardware data prefetcher that performs hardware prefetches for the predetermined program using the prefetch trait. Alternatively, the processing core loads each of one or more range registers of the processor with a respective address range in response to detecting that the predetermined program is running on the processor. Each of the one or more address ranges has an associated prefetch trait, wherein the prefetch trait is either exclusive or shared. The hardware data prefetcher performs hardware prefetches for the predetermined program using the prefetch traits associated with the address ranges loaded into the range registers.

公开(公告)号：US09507597B2

公开(公告)日：2016-11-29

申请号：US14165354

申请日：2014-01-27

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  Terry Parks ,  John Michael Greer

IPC: G06F9/00 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/3848 ,  G06F9/3851

Abstract: A microprocessor includes a predicting unit and a control unit. The control unit controls the predicting unit to accumulate a history of characteristics of executed instructions and makes predictions related to subsequent instructions based on the history while the microprocessor is running a first thread. The control unit also detects a transition from running the first thread to running a second thread and controls the predicting unit to selectively suspend accumulating the history and making the predictions using the history while running the second thread. The predicting unit makes static predictions while running the second thread. The selectivity may be based on the privilege level, identity or length of the second thread, static prediction effectiveness during a previous execution instance of the thread, whether the transition was made due to a system call, and whether the second thread is an interrupt handler.

Abstract translation: 微处理器包括预测单元和控制单元。 控制单元控制预测单元累积执行指令的特征历史，并且在微处理器运行第一线程的同时基于历史来进行与后续指令相关的预测。 控制单元还检测从运行第一线程到运行第二线程的转变，并且控制预测单元选择性地暂停累积历史并且在运行第二线程时使用历史进行预测。 预测单元在运行第二个线程时进行静态预测。 选择性可以基于第二线程的特权级别，身份或长度，线程的先前执行实例期间的静态预测有效性，是否由于系统调用而进行转换，以及第二线程是否是中断处理程序 。

公开(公告)号：US20140365753A1

公开(公告)日：2014-12-11

申请号：US14165354

申请日：2014-01-27

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  Terry Parks ,  John Michael Greer

IPC: G06F9/30

CPC classification number: G06F9/30058 ,  G06F9/3848 ,  G06F9/3851

Abstract: A microprocessor includes a predicting unit and a control unit. The control unit controls the predicting unit to accumulate a history of characteristics of executed instructions and makes predictions related to subsequent instructions based on the history while the microprocessor is running a first thread. The control unit also detects a transition from running the first thread to running a second thread and controls the predicting unit to selectively suspend accumulating the history and making the predictions using the history while running the second thread. The predicting unit makes static predictions while running the second thread. The selectivity may be based on the privilege level, identity or length of the second thread, static prediction effectiveness during a previous execution instance of the thread, whether the transition was made due to a system call, and whether the second thread is an interrupt handler.

Abstract translation: 微处理器包括预测单元和控制单元。 控制单元控制预测单元累积执行指令的特征历史，并且在微处理器运行第一线程的同时基于历史来进行与后续指令相关的预测。 控制单元还检测从运行第一线程到运行第二线程的转变，并且控制预测单元选择性地暂停累积历史并且在运行第二线程时使用历史进行预测。 预测单元在运行第二个线程时进行静态预测。 选择性可以基于第二线程的特权级别，身份或长度，线程的先前执行实例期间的静态预测有效性，是否由于系统调用而进行转换，以及第二线程是否是中断处理程序 。

公开(公告)号：US09891916B2

公开(公告)日：2018-02-13

申请号：US14624981

申请日：2015-02-18

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  Albert J. Loper ,  John Michael Greer ,  Meera Ramani-Augustin

IPC: G06F9/30 ,  G06F12/08 ,  G06F3/06 ,  G06F12/0862 ,  G06F12/0831 ,  G06F12/0842 ,  G06F12/084

CPC classification number: G06F9/30047 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/30109 ,  G06F9/3802 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0862 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/6022 ,  G06F2212/6024

Abstract: A hardware data prefetcher is comprised in a memory access agent, wherein the memory access agent is one of a plurality of memory access agents that share a memory. The hardware data prefetcher includes a prefetch trait that is initially either exclusive or shared. The hardware data prefetcher also includes a prefetch module that performs hardware prefetches from a memory block of the shared memory using the prefetch trait. The hardware data prefetcher also includes an update module that performs analysis of accesses to the memory block by the plurality of memory access agents and, based on the analysis, dynamically updates the prefetch trait to either exclusive or shared while the prefetch module performs hardware prefetches from the memory block using the prefetch trait.

公开(公告)号：US09483406B2

公开(公告)日：2016-11-01

申请号：US14315064

申请日：2014-06-25

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  John Michael Greer

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/383 ,  G06F2212/502 ,  G06F2212/6026

Abstract: A microprocessor includes a first hardware data prefetcher that prefetches data into the microprocessor according to a first algorithm. The microprocessor also includes a second hardware data prefetcher that prefetches data into the microprocessor according to a second algorithm, wherein the first and second algorithms are different. The second prefetcher detects that it is prefetching data into the microprocessor according to the second algorithm in excess of a first predetermined rate and, in response, sends a throttle indication to the first prefetcher. The first prefetcher prefetches data into the microprocessor according to the first algorithm at below a second predetermined rate in response to receiving the throttle indication from the second prefetcher.

Abstract translation: 微处理器包括根据第一算法将数据预取到微处理器的第一硬件数据预取器。 微处理器还包括第二硬件数据预取器，其根据第二算法将数据预取到微处理器中，其中第一和第二算法是不同的。 第二预取器检测到根据第二算法将数据预取到微处理器中超过第一预定速率，并且作为响应，向第一预取器发送节气门指示。 响应于从第二预取器接收到节气门指示，第一预取器根据第一算法在低于第二预定速率的情况下将数据预取到微处理器中。

公开(公告)号：US08880807B2

公开(公告)日：2014-11-04

申请号：US14282420

申请日：2014-05-20

Applicant: VIA Technologies, Inc.

Inventor： Rodney E. Hooker ,  John Michael Greer

IPC: G06F12/00 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F9/3814 ,  G06F12/0862 ,  G06F2212/602 ,  G06F2212/6026

Abstract: A data prefetcher in a microprocessor. The data prefetcher includes a plurality of period match counters associated with a corresponding plurality of different pattern periods. The data prefetcher also includes control logic that updates the plurality of period match counters in response to accesses to a memory block by the microprocessor, determines a clear pattern period based on the plurality of period match counters and prefetches into the microprocessor non-fetched cache lines within the memory block based on a pattern having the clear pattern period determined based on the plurality of period match counters.

Abstract translation: 微处理器中的数据预取器。 数据预取器包括与相应的多个不同模式周期相关联的多个周期匹配计数器。 数据预取器还包括响应于微处理器对存储器块的访问而更新多个周期匹配计数器的控制逻辑，基于多个周期匹配计数器确定清除模式周期，并预取到微处理器未获取的高速缓存行 基于具有基于多个周期匹配计数器确定的清除模式周期的模式在存储块内。

公开(公告)号：US20140289479A1

公开(公告)日：2014-09-25

申请号：US14282420

申请日：2014-05-20

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  John Michael Greer

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F9/3814 ,  G06F12/0862 ,  G06F2212/602 ,  G06F2212/6026

Abstract: A data prefetcher in a microprocessor. The data prefetcher includes a plurality of period match counters associated with a corresponding plurality of different pattern periods. The data prefetcher also includes control logic that updates the plurality of period match counters in response to accesses to a memory block by the microprocessor, determines a clear pattern period based on the plurality of period match counters and prefetches into the microprocessor non-fetched cache lines within the memory block based on a pattern having the clear pattern period determined based on the plurality of period match counters.

Abstract translation: 微处理器中的数据预取器。 数据预取器包括与相应的多个不同模式周期相关联的多个周期匹配计数器。 数据预取器还包括响应于微处理器对存储器块的访问而更新多个周期匹配计数器的控制逻辑，基于多个周期匹配计数器确定清除模式周期，并预取到微处理器未获取的高速缓存行 基于具有基于多个周期匹配计数器确定的清除模式周期的模式在存储块内。

公开(公告)号：US09251083B2

公开(公告)日：2016-02-02

申请号：US13792428

申请日：2013-03-11

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  John Michael Greer

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/6026

Abstract: A microprocessor includes a first and second hardware data prefetchers configured to prefetch data into the microprocessor according to first and second respective algorithms, which are different. The second prefetcher is configured to detect a memory access pattern within a memory region and responsively prefetch data from the memory region according the second algorithm. The second prefetcher is further configured to provide to the first prefetcher a descriptor of the memory region. The first prefetcher is configured to stop prefetching data from the memory region in response to receiving the descriptor of the memory region from the second prefetcher. The second prefetcher also provides to the first prefetcher a communication to resume prefetching data from the memory region, such as when the second prefetcher subsequently detects that a predetermined number of memory accesses to the memory region are not in the memory access pattern.

Abstract translation: 微处理器包括第一和第二硬件数据预取器，其被配置为根据不同的第一和第二相应算法将数据预取入微处理器。 第二预取器被配置为检测存储器区域内的存储器访问模式，并且根据第二算法响应地从存储器区域预取数据。 第二预取器还被配置为向第一预取器提供存储器区域的描述符。 响应于从第二预取器接收到存储器区域的描述符，第一预取器被配置为停止从存储器区域预取数据。 第二预取器还向第一预取器提供通信以恢复从存储器区域预取数据，例如当第二预取器随后检测到对存储器区域的预定数量的存储器访问不在存储器访问模式中时。

公开(公告)号：US20140258641A1

公开(公告)日：2014-09-11

申请号：US13792428

申请日：2013-03-11

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  John Michael Greer

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/6026

Abstract: A microprocessor includes a first and second hardware data prefetchers configured to prefetch data into the microprocessor according to first and second respective algorithms, which are different. The second prefetcher is configured to detect a memory access pattern within a memory region and responsively prefetch data from the memory region according the second algorithm. The second prefetcher is further configured to provide to the first prefetcher a descriptor of the memory region. The first prefetcher is configured to stop prefetching data from the memory region in response to receiving the descriptor of the memory region from the second prefetcher. The second prefetcher also provides to the first prefetcher a communication to resume prefetching data from the memory region, such as when the second prefetcher subsequently detects that a predetermined number of memory accesses to the memory region are not in the memory access pattern.

Abstract translation: 微处理器包括第一和第二硬件数据预取器，其被配置为根据不同的第一和第二相应算法将数据预取入微处理器。 第二预取器被配置为检测存储器区域内的存储器访问模式，并且根据第二算法响应地从存储器区域预取数据。 第二预取器还被配置为向第一预取器提供存储器区域的描述符。 响应于从第二预取器接收到存储器区域的描述符，第一预取器被配置为停止从存储器区域预取数据。 第二预取器还向第一预取器提供通信以恢复从存储器区域预取数据，例如当第二预取器随后检测到对存储器区域的预定数量的存储器访问不在存储器访问模式中时。

公开(公告)号：US20140310479A1

公开(公告)日：2014-10-16

申请号：US14315064

申请日：2014-06-25

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  John Michael Greer

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/383 ,  G06F2212/502 ,  G06F2212/6026

Abstract: A microprocessor includes a first hardware data prefetcher that prefetches data into the microprocessor according to a first algorithm. The microprocessor also includes a second hardware data prefetcher that prefetches data into the microprocessor according to a second algorithm, wherein the first and second algorithms are different. The second prefetcher detects that it is prefetching data into the microprocessor according to the second algorithm in excess of a first predetermined rate and, in response, sends a throttle indication to the first prefetcher. The first prefetcher prefetches data into the microprocessor according to the first algorithm at below a second predetermined rate in response to receiving the throttle indication from the second prefetcher.

Abstract translation: 微处理器包括根据第一算法将数据预取到微处理器的第一硬件数据预取器。 微处理器还包括第二硬件数据预取器，其根据第二算法将数据预取到微处理器中，其中第一和第二算法是不同的。 第二预取器检测到根据第二算法将数据预取到微处理器中超过第一预定速率，并且作为响应，向第一预取器发送节气门指示。 响应于从第二预取器接收到节气门指示，第一预取器根据第一算法在低于第二预定速率的情况下将数据预取到微处理器中。