公开(公告)号：US20060267106A1

公开(公告)日：2006-11-30

申请号：US11137495

申请日：2005-05-26

申请人： Donald Chao ,  Chien-Hao Chen ,  Ling-Yen Yeh ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Donald Chao ,  Chien-Hao Chen ,  Ling-Yen Yeh ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L29/772

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A semiconductor device includes a substrate, a gate structure over the substrate, a first sidewall spacer on a sidewall of the gate structure, a first diffusion region in the substrate and adjacent to the gate structure, the first sidewall spacer and the first diffusion region being on one side of the gate structure, and a first conductive layer in the first diffusion region, the first conductive layer being spaced apart from the first sidewall spacer.

摘要翻译： 半导体器件包括衬底，衬底上的栅极结构，栅极结构的侧壁上的第一侧壁间隔物，衬底中的第一扩散区域和栅极结构附近，第一侧壁间隔物和第一扩散区域是 在所述栅极结构的一侧，以及所述第一扩散区域中的第一导电层，所述第一导电层与所述第一侧壁间隔物间隔开。

公开(公告)号：US20060099771A1

公开(公告)日：2006-05-11

申请号：US10970090

申请日：2004-10-21

申请人： Chien-Hao Chen ,  Vincent Chang ,  Ji-Yi Yang ,  Chia-Lin Chen ,  Tze-Liang Lee

发明人： Chien-Hao Chen ,  Vincent Chang ,  Ji-Yi Yang ,  Chia-Lin Chen ,  Tze-Liang Lee

IPC分类号： H01L21/76

CPC分类号： H01L21/76232

摘要： A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said exposed substrate portions only; backfilling the STI trench with a second insulating layer; planarizing the second insulating layer; and, carrying out a wet etching process to remove the uppermost hardmask layer.

摘要翻译： 一种用于形成无自由度的氮化物衬底浅沟槽隔离（STI）特征的方法，包括提供包括延伸穿过最上面的硬掩模层的STI沟槽的衬底，暴露衬底部分的衬底的厚度; 仅在所述暴露的衬底部分上选择性地形成衬在STI沟槽上的第一绝缘层; 用第二绝缘层回填STI槽; 平面化第二绝缘层; 并进行湿蚀刻处理以去除最上面的硬掩模层。

公开(公告)号：US20100015814A1

公开(公告)日：2010-01-21

申请号：US12176655

申请日：2008-07-21

申请人： Chien-Hao Chen ,  Pang-Yen Tsai ,  Chie-Chien Chang ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chien-Hao Chen ,  Pang-Yen Tsai ,  Chie-Chien Chang ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L21/31

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/45 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source/drain regions, wherein the stress-inducing layer comprises a first semiconductor material and a second semiconductor material. A treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material and the second semiconductor material is forced lower into the stress-inducing layer. The stress-inducing layer may be either a recessed region or non-recessed region. A first method involves forming a stress-inducing layer, such as SiGe, in the source/drain regions and performing a nitridation or oxidation process. A nitride or oxide film is formed in the top portion of the stress-inducing layer, forcing the Ge lower into the stress-inducing layer. Another method embodiment involves forming a reaction layer over the stress-inducing layer and performing a treatment process to cause the reaction layer to react with the stress-inducing layer.

摘要翻译： 提供具有局部应力的MOSFET。 MOSFET具有形成在源极/漏极区域中的应力诱导层，其中应力诱导层包括第一半导体材料和第二半导体材料。 对应力诱导层进行处理，使得由第一半导体材料引起反应，并且第二半导体材料被迫下降到应力诱导层中。 应力诱导层可以是凹陷区域或非凹陷区域。 第一种方法包括在源极/漏极区域中形成诸如SiGe的应力诱导层并进行氮化或氧化过程。 在应力诱导层的顶部形成氮化物或氧化物膜，迫使Ge较低进入应力诱导层。 另一方法实施例涉及在应力诱导层上形成反应层，并进行处理工艺以使反应层与应力诱导层反应。

公开(公告)号：US07528028B2

公开(公告)日：2009-05-05

申请号：US11199011

申请日：2005-08-08

申请人： Mong Song Liang ,  Chien-Hao Chen ,  Chun-Feng Nieh ,  Pang-Yen Tsai ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Mong Song Liang ,  Chien-Hao Chen ,  Chun-Feng Nieh ,  Pang-Yen Tsai ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L21/8238

CPC分类号： H01L21/823412 ,  H01L21/7624 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A method for forming a semiconductor structure includes providing a substrate, forming a first device region on the substrate, forming a stressor layer overlying the first device region, and super annealing the stressor layer in the first device region, preferably by exposing the substrate to a high-energy radiance source, so that the stressor layer is super annealed for a substantially short duration. Preferably, the method further includes masking a second device region on the substrate while the first device region is super annealed. Alternatively, after the stressor layer in the first region is annealed, the stressor layer in the second device region is super annealed. A semiconductor structure formed using the method has different strains in the first and second device regions.

摘要翻译： 一种用于形成半导体结构的方法包括：提供衬底，在衬底上形成第一器件区域，形成覆盖第一器件区域的应力层，以及对第一器件区域中的应力层进行超退火，优选通过将衬底暴露于 高能量辐射源，使得应力层在超短时间内进行超退火。 优选地，该方法还包括在第一器件区域被超退火时掩蔽衬底上的第二器件区域。 或者，在第一区域中的应力层退火之后，第二器件区域中的应力层被超退火。 使用该方法形成的半导体结构在第一和第二器件区域中具有不同的应变。

公开(公告)号：US07335544B2

公开(公告)日：2008-02-26

申请号：US11012413

申请日：2004-12-15

申请人： Chien-Hao Chen ,  Donald Y. Chao ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chien-Hao Chen ,  Donald Y. Chao ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L29/739

CPC分类号： H01L29/7833 ,  H01L29/6659 ,  H01L29/7843

摘要： A metal-oxide-semiconductor field-effect transistors (MOSFET) having localized stressors is provided. In accordance with embodiments of the present invention, a transistor comprises a high-stress film over the source/drain regions, but not over the gate electrode. The high-stress film may be a tensile-stress film for use with n-channel devices or a compressive-stress film for use with p-channel devices. A method of fabricating a MOSFET with localized stressors over the source/drain regions comprises forming a transistor having a gate electrode and source/drain regions, forming a high-stress film over the gate electrode and the source/drain regions, and thereafter removing the high-stress film located over the gate electrode, thereby leaving the high-stress film located over the source/drain regions. A contact-etch stop layer may be formed over the transistor.

摘要翻译： 提供了具有局部应力源的金属氧化物半导体场效应晶体管（MOSFET）。 根据本发明的实施例，晶体管包括源/漏区上的高应力膜，但不在栅电极上。 高应力膜可以是用于n沟道器件的拉伸应力膜或用于p沟道器件的压应力膜。 在源极/漏极区域上制造具有局部应力源的MOSFET的方法包括形成具有栅电极和源极/漏极区的晶体管，在栅电极和源极/漏极区上形成高应力膜，然后除去 高应力膜位于栅电极之上，从而使高应力膜位于源极/漏极区之上。 接触蚀刻停止层可以形成在晶体管上。

公开(公告)号：US20070063282A1

公开(公告)日：2007-03-22

申请号：US11599931

申请日：2006-11-15

申请人： Ji-Yi Yang ,  Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Huan-Just Lin

发明人： Ji-Yi Yang ,  Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Huan-Just Lin

IPC分类号： H01L27/12 ,  H01L29/00

CPC分类号： H01L21/3247 ,  H01L21/76232 ,  H01L21/76283 ,  H01L27/1203

摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.

摘要翻译： 通过退火将体硅转变成SOI样结构。 沟槽形成在大量衬底中以限定器件位置。 沟槽的下部在氢气气氛中在低压下退火。 这将下沟槽部分转变成在器件位置下延伸的膨胀的球状空隙。 相邻的空洞每个居住在中间位置的一半左右。 消耗硅的过程在空隙的壁上形成衬垫，相邻空隙上的衬垫邻接以将介入的器件位置与衬底和其它器件位置隔离。

公开(公告)号：US20060284249A1

公开(公告)日：2006-12-21

申请号：US11157515

申请日：2005-06-21

申请人： Chien-Hao Chen ,  Chun-Feng Nieh ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chien-Hao Chen ,  Chun-Feng Nieh ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L21/8238

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A pMOS transistor having reduced diffusion from source/drain regions and a method of forming the same are provided. The pMOS transistor includes a source/drain region doped with a p-type impurity and a diffusion-retarding material in a semiconductor substrate. The pMOS transistor further includes a gate dielectric over a channel region in the semiconductor substrate, a gate electrode over the gate dielectric, and a lightly doped source/drain (LDD) region substantially aligned with an edge of the gate electrode. The diffusion-retarding material preferably includes carbon, fluorine, nitrogen, and combinations thereof.

摘要翻译： 提供了具有从源极/漏极区域的扩散减小的pMOS晶体管及其形成方法。 pMOS晶体管包括掺杂有p型杂质的源极/漏极区域和在半导体衬底中的扩散阻滞材料。 pMOS晶体管还包括在半导体衬底中的沟道区域上的栅极电介质，栅极电介质上的栅极电极以及基本上与栅电极的边缘对齐的轻掺杂源极/漏极（LDD）区域。 扩散阻滞材料优选包括碳，氟，氮及其组合。

公开(公告)号：US08673736B2

公开(公告)日：2014-03-18

申请号：US11546768

申请日：2006-10-12

申请人： Ji-Yi Yang ,  Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Huan-Just Lin

发明人： Ji-Yi Yang ,  Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Huan-Just Lin

IPC分类号： H01L21/762

CPC分类号： H01L21/3247 ,  H01L21/76232 ,  H01L21/76283 ,  H01L27/1203

摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.

摘要翻译： 通过退火将体硅转变成SOI样结构。 沟槽形成在大量衬底中以限定器件位置。 沟槽的下部在氢气气氛中在低压下退火。 这将下沟槽部分转变成在器件位置下延伸的膨胀的球状空隙。 相邻的空洞每个居住在中间位置的一半左右。 消耗硅的过程在空隙的壁上形成衬垫，相邻空隙上的衬垫邻接以将介入的器件位置与衬底和其它器件位置隔离。

公开(公告)号：US07494857B2

公开(公告)日：2009-02-24

申请号：US11648371

申请日：2006-12-29

申请人： Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ting Wang ,  Hsun Chang

发明人： Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ting Wang ,  Hsun Chang

IPC分类号： H01L21/336 ,  H01L21/461

CPC分类号： H01L21/268 ,  H01L21/324 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode on the gate dielectric; forming a source/drain region adjacent the gate dielectric and the gate electrode; forming an absorption-capping layer over the source/drain region and the gate electrode; performing an activation by applying a high-energy light to the absorption-capping layer; and removing the absorption-capping layer.

摘要翻译： 一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在栅极电介质上形成栅电极; 形成与所述栅极电介质和所述栅电极相邻的源极/漏极区域; 在源极/漏极区域和栅极电极上形成吸收覆盖层; 通过向吸收覆盖层施加高能量光来进行激活; 并去除吸收层。

公开(公告)号：US20080128765A1

公开(公告)日：2008-06-05

申请号：US12016499

申请日：2008-01-18

申请人： Chien-Hao Chen ,  Donald Y. Chao ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chien-Hao Chen ,  Donald Y. Chao ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L29/78

CPC分类号： H01L29/7833 ,  H01L29/6659 ,  H01L29/7843

摘要： A metal-oxide-semiconductor field-effect transistors (MOSFET) having localized stressors is provided. In accordance with embodiments of the present invention, a transistor comprises a high-stress film over the source/drain regions, but not over the gate electrode. The high-stress film may be a tensile-stress film for use with n-channel devices or a compressive-stress film for use with p-channel devices. A method of fabricating a MOSFET with localized stressors over the source/drain regions comprises forming a transistor having a gate electrode and source/drain regions, forming a high-stress film over the gate electrode and the source/drain regions, and thereafter removing the high-stress film located over the gate electrode, thereby leaving the high-stress film located over the source/drain regions. A contact-etch stop layer may be formed over the transistor.

摘要翻译： 提供了具有局部应力源的金属氧化物半导体场效应晶体管（MOSFET）。 根据本发明的实施例，晶体管包括源/漏区上的高应力膜，但不在栅电极上。 高应力膜可以是用于n沟道器件的拉伸应力膜或用于p沟道器件的压应力膜。 在源极/漏极区域上制造具有局部应力源的MOSFET的方法包括形成具有栅电极和源/漏区的晶体管，在栅电极和源/漏区上形成高应力膜，然后除去 高应力膜位于栅电极之上，从而使高应力膜位于源极/漏极区之上。 接触蚀刻停止层可以形成在晶体管上。