公开(公告)号：US08791018B2

公开(公告)日：2014-07-29

申请号：US11641647

申请日：2006-12-19

Applicant: Wen Yu ,  Stephen B. Robie ,  Jeremias D. Romero

Inventor： Wen Yu ,  Stephen B. Robie ,  Jeremias D. Romero

IPC: H01L21/441 ,  H01L21/443 ,  H01L21/283 ,  H01L21/285 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L21/28556 ,  H01L21/2855 ,  H01L21/76841 ,  H01L23/53228 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50° C. or less, with the deposition taking place at a power level of 300 W or less.

Abstract translation: 本发明的形成电子结构的方法包括提供钽基层并在钽层上沉积一层铜，该沉积是通过基底层温度在50℃以下的物理气相沉积进行的，其中 放电发生在300W或更小的功率水平。

公开(公告)号：US20080286921A1

公开(公告)日：2008-11-20

申请号：US11748743

申请日：2007-05-15

Applicant: Wen Yu ,  Paul Besser ,  Bin Yang ,  Haijiang Yu ,  Simon S. Chan

Inventor： Wen Yu ,  Paul Besser ,  Bin Yang ,  Haijiang Yu ,  Simon S. Chan

IPC: H01L21/8234

CPC classification number: H01L21/324 ,  H01L21/28052 ,  H01L29/66507 ,  H01L29/78

Abstract: The gate and active regions of a device are formed and alternating steps of applying and removing nitride and oxide layers allows exposing silicon in different areas while keeping silicon or polysilicon in other area covered with nitride. Metal layers are deposited over the exposed silicon or polysilicon and annealing forms a silicide layer in the selected exposed areas. The oxide and/or nitride layers are removed from the covered areas and another metal layer is deposited. The anneal process is repeated with silicide of one thickness formed over the second exposed areas with additional thickness of silicide formed over the previous silicide thickness.

Abstract translation: 形成器件的栅极和有源区，并且施加和去除氮化物和氧化物层的交替步骤允许在不同区域暴露硅，同时保持覆盖有氮化物的其它区域中的硅或多晶硅。 金属层沉积在暴露的硅或多晶硅上，退火在所选择的暴露区域中形成硅化物层。 氧化物层和/或氮化物层从被覆盖区域移除，另一个金属层被沉积​​。 在第二暴露区域上形成一层厚度的硅化物，并在先前的硅化物厚度上形成附加的硅化物厚度来重复退火工艺。

公开(公告)号：US07407882B1

公开(公告)日：2008-08-05

申请号：US10928665

申请日：2004-08-27

Applicant: Connie Pin-Chin Wang ,  Paul R. Besser ,  Wen Yu ,  Jinsong Yin ,  Keizaburo Yoshie

Inventor： Connie Pin-Chin Wang ,  Paul R. Besser ,  Wen Yu ,  Jinsong Yin ,  Keizaburo Yoshie

IPC: H01L21/4763

CPC classification number: H01L21/76843 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76856

Abstract: A semiconductor component having a titanium silicide contact structure and a method for manufacturing the semiconductor component. A layer of dielectric material is formed over a semiconductor substrate. An opening having sidewalls is formed in the dielectric layer and exposes a portion of the semiconductor substrate. Titanium silicide is disposed on the dielectric layer, sidewalls, and the exposed portion of the semiconductor substrate. The titanium silicide may be formed by disposing titanium on the dielectric layer, sidewalls, and exposed portion of the semiconductor substrate and reacting the titanium with silane. Alternatively, the titanium silicide may be sputter deposited. A layer of titanium nitride is formed on the titanium silicide. A layer of tungsten is formed on the titanium nitride. The tungsten, titanium nitride, and titanium silicide are polished to form the contact structures.

Abstract translation: 具有硅化钛接触结构的半导体部件和半导体部件的制造方法。 在半导体衬底上形成介电材料层。 在电介质层中形成具有侧壁的开口，并露出半导体衬底的一部分。 钛硅化物设置在电介质层，侧壁和半导体衬底的暴露部分上。 钛硅化物可以通过在电介质层，侧壁和半导体衬底的暴露部分上设置钛并使钛与硅烷反应而形成。 或者，可以溅射沉积钛硅化物。 在硅化钛上形成氮化钛层。 在氮化钛上形成钨层。 将钨，氮化钛和硅化钛抛光以形成接触结构。

公开(公告)号：US07319065B1

公开(公告)日：2008-01-15

申请号：US10637406

申请日：2003-08-08

Applicant: Wen Yu ,  Paul Raymond Besser

Inventor： Wen Yu ,  Paul Raymond Besser

IPC: H01L21/4763

CPC classification number: H01L21/76816 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor component having a composite via structure with an enhanced aspect ratio and a method for manufacturing the semiconductor component. Vias having a first aspect ratio are formed in a contact layer disposed on a semiconductor substrate and filled with a metal. The metal is planarized and a dielectric layer is formed over the contact layer. Via extension structures having the same aspect ratio as those in the contact layer are formed in the dielectric layer and aligned with the vias in the contact layer. The vias in the dielectric layer are filled with metal and the metal is planarized. The contact vias in the contact layer and the dielectric layer cooperate to form a composite via structure having the enhanced aspect ratio. Additional dielectric layers having via structures can be included in the composite contact structure to further enhance the aspect ratio of the via structure.

Abstract translation: 具有增强纵横比的复合通孔结构的半导体部件和半导体部件的制造方法。 具有第一纵横比的通孔形成在设置在半导体衬底上并被金属填充的接触层中。 金属被平坦化，并且在接触层上形成电介质层。 在电介质层中形成具有与接触层相同的纵横比的延伸结构，并与接触层中的通孔对准。 电介质层中的通孔用金属填充，金属被平坦化。 接触层和电介质层中的接触孔合作形成具有增强的纵横比的复合通孔结构。 具有通孔结构的附加电介质层可以包括在复合接触结构中，以进一步增强通孔结构的纵横比。

公开(公告)号：US07306988B1

公开(公告)日：2007-12-11

申请号：US11063138

申请日：2005-02-22

Applicant: Steven C. Avanzino ,  Wen Yu

Inventor： Steven C. Avanzino ,  Wen Yu

IPC: H01L21/8242

CPC classification number: H01L45/085 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608

Abstract: Methods of making memory devices/cells are disclosed. A memory cell contains first and second electrode layers and a controllably conductive media therebetween. The controllably conductive media contains a copper sulfide-containing passive layer and active layer containing a Cu-doped tantalum oxide and/or titanium oxide layer. Methods of using the memory devices/cells, and devices such as computers containing the memory devices/cells are also disclosed.

Abstract translation: 公开了制造存储器件/单元的方法。 存储单元包含第一和第二电极层以及它们之间的可控导电介质。 可控导电介质包含含硫化铜的钝化层和含有Cu掺杂的氧化钽和/或氧化钛层的有源层。 还公开了使用存储器件/单元的方法，以及诸如包含存储器件/单元的计算机的器件。

公开(公告)号：US07057454B2

公开(公告)日：2006-06-06

申请号：US10855861

申请日：2004-05-27

Applicant: Fan Yang Ma ,  Wen Yu

Inventor： Fan Yang Ma ,  Wen Yu

IPC: H03F1/36

CPC classification number: H03G1/0088

Abstract: A DSM variable high-gain circuit includes a differential amplifier and a negative feedback loop comprising low resistance poly resistors and switches configured in a T-structure having a junction point as part of the negative feedback loop. A third resistor branch of the T-structure includes a switch that connects the junction point through the third resistor branch to ground when in a closed state and that turns the third resistor branch into an open circuit when in an open state The switch of the third resistor branch, when in the closed state, produces a gain at the output of the variable high-gain circuit.

Abstract translation: DSM可变高增益电路包括差分放大器和负反馈回路，其包括以具有作为负反馈回路的一部分的连接点的T形结构中配置的低电阻多电阻器和开关。 T型结构的第三电阻器支路包括开关，当处于闭合状态时，将通过第三电阻器分支的接合点连接到地，并且当处于断开状态时将第三电阻器分支转变为开路。第三个开关 当处于闭合状态时，电阻分支在可变高增益电路的输出端产生增益。

公开(公告)号：US20060070724A1

公开(公告)日：2006-04-06

申请号：US10959360

申请日：2004-10-06

Applicant: Wen Yu ,  Ramchandra Patel

Inventor： Wen Yu ,  Ramchandra Patel

IPC: F28F19/00

CPC classification number: F25B39/04 ,  F25B2339/0441 ,  F25B2400/162

Abstract: A heat exchanger for a vehicle is provided having a core with a set of flow tubes connected to a header. The header includes a receiver/dryer housing in fluid communication with the flow tubes. An insert assembly is received in an end of the receiver/dryer housing and includes a sleeve having a substantially smooth outer surface, a filter portion received within the sleeve, and a plug portion configured to form a substantially fluid-tight seal with the sleeve. The inner diameter of the receiver/dryer housing and the outer diameter of the sleeve are substantially equal to each other.

Abstract translation: 提供了一种用于车辆的热交换器，其具有与一个连接到集管的一组流管的芯体。 集管包括与流管流体连通的接收器/干燥器壳体。 插入组件被容纳在接收器/干燥器壳体的端部中并且包括具有基本平滑的外表面的套筒，容纳在套筒内的过滤器部分以及被配置为与套筒形成基本上不透液密封的插塞部分。 接收器/干燥器壳体的内径和套筒的外径基本相等。