公开(公告)号：US20090113172A1

公开(公告)日：2009-04-30

申请号：US12121941

申请日：2008-05-16

申请人： Martin M. Deneroff ,  Gregory M. Thorson ,  Randal S. Passint

发明人： Martin M. Deneroff ,  Gregory M. Thorson ,  Randal S. Passint

IPC分类号： G06F9/02

CPC分类号： G06F15/17312 ,  G06F15/17343 ,  G06F15/17381 ,  H04L45/14 ,  H04L67/1002

摘要： A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.

摘要翻译： 提供了一种用于在可扩展多处理器系统内互连多个处理元件节点的系统和方法。 每个处理元件节点包括至少一个处理器和存储器。 可扩展互连网络包括互连集群中的处理元件节点的物理通信链路。 可伸缩互连网络中的第一组路由器在多个处理单元节点之间路由消息。 可扩展互连网络中的一个或多个元变换器在第一组路由器之间路由消息，使得第一集群中的每个路由器通过一个或多个元变换器连接到所有其他集群。

公开(公告)号：US07464115B2

公开(公告)日：2008-12-09

申请号：US11113805

申请日：2005-04-25

申请人： John Carter ,  Randal S. Passint ,  Donglai Dai ,  Zhen Fang ,  Lixin Zhang ,  Gregory M. Thorson

发明人： John Carter ,  Randal S. Passint ,  Donglai Dai ,  Zhen Fang ,  Lixin Zhang ,  Gregory M. Thorson

IPC分类号： G06F13/42

CPC分类号： G06F15/16 ,  Y10S707/99952

摘要： A method and apparatus for controlling access by a set of accessing nodes to memory of a home node (in a multimode computer system) determines that each node in the set of nodes has accessed the memory, and forwards a completion message to each node in the set of nodes after it is determined that each node has accessed the memory. The completion message has data indicating that each node in the set of nodes has accessed the memory of the home node.

摘要翻译： 用于控制一组访问节点对家庭节点（在多模式计算机系统中）的存储器的访问的方法和装置确定该组节点中的每个节点已经访问了存储器，并将完成消息转发到 在确定每个节点已访问存储器之后，节点集合。 完成消息具有指示节点集合中的每个节点已经访问了家庭节点的存储器的数据。

公开(公告)号：US07248635B1

公开(公告)日：2007-07-24

申请号：US09620373

申请日：2000-07-20

申请人： Michael R. Arneson ,  Terrance L. Bowman ,  Frank N. Cornett ,  John F. DeRyckere ,  Brian T. Hillert ,  Philip N. Jenkins ,  Nan Ma ,  Joseph M. Placek ,  Rodney Ruesch ,  Gregory M. Thorson

发明人： Michael R. Arneson ,  Terrance L. Bowman ,  Frank N. Cornett ,  John F. DeRyckere ,  Brian T. Hillert ,  Philip N. Jenkins ,  Nan Ma ,  Joseph M. Placek ,  Rodney Ruesch ,  Gregory M. Thorson

IPC分类号： H04B3/00 ,  H03H7/38

CPC分类号： H04L25/03878 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0292

摘要： The present invention is directed toward a communications channel comprising a link level protocol, a driver, a receiver, and a canceller/equalizer. The link level protocol provides logic for DC-free signal encoding and recovery as well as supporting many features including CRC error detection and message resend to accommodate infrequent bit errors across the medium. The canceller/equalizer provides equalization for destabilized data signals and also provides simultaneous bi-directional data transfer. The receiver provides bit deskewing by removing synchronization error, or skewing, between data signals. The driver provides impedance controlling by monitoring the characteristics of the communications medium, like voltage or temperature, and providing a matching output impedance in the signal driver so that fewer distortions occur while the data travels across the communications medium.

摘要翻译： 本发明涉及包括链路级协议，驱动器，接收机和消除器/均衡器的通信信道。 链路级协议提供了无DC信号编码和恢复的逻辑，并支持许多功能，包括CRC错误检测和消息重发，以适应介质上不常见的位错误。 消除器/均衡器为不稳定的数据信号提供均衡，并且还提供同时的双向数据传输。 接收器通过消除数据信号之间的同步错误或倾斜来提供位去偏移。 驱动器通过监视通信介质的特性（如电压或温度）以及在信号驱动器中提供匹配的输出阻抗来提供阻抗控制，以便在数据传播通过通信介质时发生较少的失真。

公开(公告)号：US6055618A

公开(公告)日：2000-04-25

申请号：US550992

申请日：1995-10-31

申请人： Gregory M. Thorson

发明人： Gregory M. Thorson

IPC分类号： G06F15/177 ,  G06F15/163 ,  G06F15/17 ,  G06F15/173 ,  G06F15/80 ,  H04L12/24 ,  H04L12/56 ,  G06F15/16 ,  H04L12/00

CPC分类号： G06F15/17337

摘要： A multiprocessor computer system includes processing element nodes interconnected with physical communication links in an n-dimensional topology. A flow controlled virtual channel has virtual channel buffers assigned to each physical communication link to store packets containing information to be transferred between the processing element nodes. A non-flow controlled virtual maintenance channel has maintenance channel buffers assigned to each physical communication link to store packets of maintenance information to be transferred between the processing element nodes. The virtual maintenance channel is assigned a higher priority for accessing the physical communication links than the flow controlled virtual channel.

摘要翻译： 多处理器计算机系统包括与n维拓扑中的物理通信链路互连的处理元件节点。 流控虚拟通道具有分配给每个物理通信链路的虚拟通道缓冲器，以存储包含要在处理元件节点之间传送的信息的分组。 非流控制的虚拟维护通道具有分配给每个物理通信链路的维护通道缓冲器，以存储要在处理元件节点之间传送的维护信息的分组。 虚拟维护通道被分配了比流量控制的虚拟通道更高的访问物理通信链路的优先级。

公开(公告)号：US5721921A

公开(公告)日：1998-02-24

申请号：US450251

申请日：1995-05-25

申请人： Richard E. Kessler ,  Steven M. Oberlin ,  Gregory M. Thorson

发明人： Richard E. Kessler ,  Steven M. Oberlin ,  Gregory M. Thorson

IPC分类号： G06F9/46 ,  G06F13/38 ,  G06F15/16

CPC分类号： G06F9/52

摘要： Method and apparatus for facilitating barrier and eureka synchronization in a massively parallel processing system. The present barrier/eureka mechanism provides a partitionable, low-latency, immediately reusable, robust mechanism which can operate on a physical data-communications network and can be used to alert all processor entities (PEs) in a partition when all of the PEs in that partition have reached a designated barrier point in their individual program code, or when any one of the PEs in that partition has reached a designated eureka point in its individual program code, or when either the barrier or eureka requirements have been satisfied, which ever comes first. Multiple overlapping barrier/eureka synchronization partitions are available simultaneously through the use of a plurality of parallel barrier/eureka synchronization domains. The present barrier/eureka mechanism may be implemented on either a dedicated barrier network, or superimposed as a virtual barrier/eureka network operating on a physical data-communications network which is also used for data interchange, operating system functions, and other purposes.

摘要翻译： 用于在大规模并行处理系统中促进障碍和尤里卡同步的方法和装置。 当前的屏障/尤里卡机制提供了一种可分割的，低延迟的，立即可重用的鲁棒机制，其可以在物理数据通信网络上操作，并且可以用于警告分区中的所有处理器实体（PE），当所有PE 该分区已经到达其个别程序代码中的指定障碍点，或者当该分区中的任何一个PE在其各自的程序代码中达到指定的尤里卡点时，或者当满足屏障或尤里卡要求时，哪一个 先到 多个重叠的屏障/尤里卡同步分区可以通过使用多个并行屏障/尤里卡同步域来同时获得。 本势垒/尤里卡机制可以在专用屏障网络上实现，或者叠加在操作在物理数据通信网络上的虚拟屏障/尤里卡网络上，物理数据通信网络也用于数据交换，操作系统功能和其他目的。

公开(公告)号：US5701416A

公开(公告)日：1997-12-23

申请号：US421566

申请日：1995-04-13

申请人： Gregory M. Thorson ,  Steven L. Scott

发明人： Gregory M. Thorson ,  Steven L. Scott

IPC分类号： G06F15/173 ,  G06F15/80 ,  G06F15/16

CPC分类号： G06F15/17331 ,  G06F15/17381

摘要： A routing mechanism includes two acyclic non-adaptive virtual channels having two types of virtual channel buffers to store packets along deterministic virtual paths between nodes in an n-dimensional networked system, and an adaptive virtual channel having a third type of virtual channel buffer to store the packets along non-deterministic virtual paths between the nodes. The packets are routed between the nodes along either selected portions of the deterministic virtual paths or selected portions of the non-deterministic virtual paths based on routing information such that a packet is never routed on a selected portion of one of the non-deterministic virtual paths unless the third type virtual channel buffer associated with the selected portion of the one non-deterministic virtual path has sufficient space available to store the entire packet.

摘要翻译： 路由机制包括两个非循环非自适应虚拟信道，其具有两种类型的虚拟信道缓冲器，用于沿着n维网络系统中的节点之间的确定性虚拟路径存储分组，以及具有第三类型虚拟信道缓冲器以存储的自适应虚拟信道 节点之间的非确定性虚拟路径的数据包。 基于路由信息，分组沿着确定性虚拟路径的所选部分或非确定性虚拟路径的选定部分在节点之间路由，使得分组绝不在非确定性虚拟路径之一的所选部分上路由 除非与所述一个非确定性虚拟路径的选定部分相关联的第三类型虚拟通道缓冲器具有足够的可用于存储整个分组的空间。