公开(公告)号：US07215149B1

公开(公告)日：2007-05-08

申请号：US11012550

申请日：2004-12-15

申请人： William B. Andrews ,  Larry R. Fenstermaker ,  John Schadt ,  Mou C. Lin

发明人： William B. Andrews ,  Larry R. Fenstermaker ,  John Schadt ,  Mou C. Lin

IPC分类号： H03K19/0175

CPC分类号： H03K19/00384 ,  H03K3/356104 ,  H03K19/018521

摘要： An electrical system has a master circuit and an interface (I/F) circuit. The master circuit generates a master output signal. The I/F circuit receives an I/F input signal and a flag signal and generates an I/F output signal for application to a slave circuit, wherein the I/F input signal is based on the master output signal, and the interface circuit generates the L/F output signal either dependent on or independent of the I/F input signal as indicated by the flag signal.

摘要翻译： 电气系统具有主电路和接口（I / F）电路。 主电路产生主输出信号。 I / F电路接收I / F输入信号和标志信号，并产生用于应用于从电路的I / F输出信号，其中I / F输入信号基于主输出信号，并且接口电路 产生依赖于或独立于I / F输入信号的L / F输出信号，如标志信号所示。

公开(公告)号：US06943582B1

公开(公告)日：2005-09-13

申请号：US10671363

申请日：2003-09-25

申请人： William B. Andrews ,  Mou C. Lin ,  John Schadt

发明人： William B. Andrews ,  Mou C. Lin ,  John Schadt

IPC分类号： H03K19/177

CPC分类号： H03K19/17744

摘要： A programmable device such as a field-programmable gate array (FPGA) has programmable I/O circuitry. In one embodiment, a programmable I/O circuit (PIC) associated with at least first and second pads of the device has an output buffer that is selectively connected to the first and second pads via corresponding first and second transmission gates. The transmission gates enable an outgoing signal from the output buffer to be individually and selectively presented at the pads, while reducing the capacitive loading at each pad when the corresponding transmission gate is open (i.e., when the outgoing signal is not to be presented at that pad).

摘要翻译： 诸如现场可编程门阵列（FPGA）的可编程器件具有可编程I / O电路。 在一个实施例中，与设备的至少第一和第二焊盘相关联的可编程I / O电路（PIC）具有经由对应的第一和第二传输门选择性地连接到第一和第二焊盘的输出缓冲器。 传输门允许来自输出缓冲器的输出信号被单独地选择地呈现在焊盘处，同时当相应的传输门打开时减小每个焊盘处的容性负载（即，当不输出信号时， 垫）。

公开(公告)号：US6124732A

公开(公告)日：2000-09-26

申请号：US115683

申请日：1998-07-15

申请人： Zeljko Zilic ,  Ho T. Nguyen ,  Gary P. Powell ,  William B. Andrews ,  Richard G. Stuby, Jr.

发明人： Zeljko Zilic ,  Ho T. Nguyen ,  Gary P. Powell ,  William B. Andrews ,  Richard G. Stuby, Jr.

IPC分类号： H03K19/0185 ,  H03K19/0175

CPC分类号： H03K19/018585

摘要： The invention provides an input/output (I/O) signaling voltage range discriminator (and corresponding method) which is used to control a configurable logic device such as a configurable I/O buffer in a second electronic circuit in response to a detected signaling voltage range of a first electronic circuit. The discriminator outputs an indication of the signaling voltage range of the first electronic circuit to a configurable I/O buffer enabling it to adapt to the signaling levels used by the first electronic circuit. The I/O buffer, based on the indication provided by the discriminator, can then configure its logic to become tolerant and/or compatible with digital signals transferred to and from the first electronic circuit.

摘要翻译： 本发明提供了一种输入/输出（I / O）信令电压范围鉴别器（和相应的方法），其用于响应于检测到的信号电压来控制可配置逻辑器件，例如第二电子电路中的可配置I / O缓冲器 第一电子电路的范围。 鉴别器将第一电子电路的信号电压范围的指示输出到可配置的I / O缓冲器，使其能够适应第一电子电路使用的信号电平。 然后，基于鉴别器提供的指示，I / O缓冲器可以将它的逻辑配置成容忍和/或与传送到第一电子电路的数字信号兼容。

公开(公告)号：US08384428B1

公开(公告)日：2013-02-26

申请号：US13006622

申请日：2011-01-14

申请人： William B. Andrews ,  Zheng Chen

发明人： William B. Andrews ,  Zheng Chen

IPC分类号： H03K19/177 ,  H01L25/00

CPC分类号： H03K19/017581 ,  H03K19/17744 ,  H03K19/17776

摘要： In one embodiment of the invention, a programmable logic device, such as an FPGA, has programmable I/O circuits that can be programmed into any one of a number of different operating modes before configuration is completed. As such, the same set of I/O circuits and corresponding I/O pads can be used to configure the device using different configuration interfaces having different interface signaling requirements. Such a device may be able to be implemented using fewer I/O pads than conventional devices that employ a different set of I/O pads for each different type of configuration interface supported by the device.

摘要翻译： 在本发明的一个实施例中，诸如FPGA的可编程逻辑器件具有可编程I / O电路，其可以在配置完成之前被编程为多个不同操作模式中的任何一个。 因此，可以使用同一组I / O电路和相应的I / O焊盘来配置使用具有不同接口信令要求的不同配置接口的设备。 可以使用比由设备支持的每种不同类型的配置接口采用不同I / O焊盘组的传统设备更少的I / O焊盘来实现这样的器件。

公开(公告)号：US07535258B1

公开(公告)日：2009-05-19

申请号：US11593274

申请日：2006-11-06

申请人： Phillip L. Johnson ,  William B. Andrews ,  Gregory S. Cartney

发明人： Phillip L. Johnson ,  William B. Andrews ,  Gregory S. Cartney

IPC分类号： H03K19/0175

CPC分类号： H03K19/018585 ,  H03F3/45237 ,  H03F3/4565 ,  H03F2203/45008 ,  H03F2203/45048 ,  H03F2203/45082 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45504 ,  H03F2203/45681

摘要： A buffer for a programmable logic device has programmable current sink and source circuitry and an independently programmable common-mode voltage reference source. An amplifier, responsive to a common-mode voltage detector and the voltage reference source, forces a common-mode voltage of an output signal from the buffer to approximate the voltage from the common-mode voltage reference source.

摘要翻译： 可编程逻辑器件的缓冲器具有可编程电流吸收和源极电路以及独立可编程的共模电压参考源。 响应于共模电压检测器和电压参考源的放大器迫使来自缓冲器的输出信号的共模电压近似来自共模电压基准源的电压。

公开(公告)号：US07505752B1

公开(公告)日：2009-03-17

申请号：US11189067

申请日：2005-07-25

申请人： William B. Andrews ,  John Schadt

发明人： William B. Andrews ,  John Schadt

IPC分类号： H04B1/16 ,  H04B1/28

CPC分类号： H04L25/0272 ,  H04L25/0264 ,  H04L25/0294

摘要： In one embodiment of the invention, a receiver has two mux circuits, two receiver circuits, and a mixer. The muxes select first and second input signals for the receiver circuits. A p-type transistor in a transmission gate in each mux is connected (i) at its channel nodes between a pad and the mux output and (ii) to receive a control signal at its gate node. Control circuitry for the p-type transistor implements a threshold reduction filter that ensures that a maximum voltage level at the mux output is at least a threshold below the mux's power supply voltage. Based on first and second input signals, the first receiver circuit generates first and second intermediate signals, and the second receiver circuit generates third and fourth intermediate signals. The mixer circuit combines the intermediate signals to generate first and second output signals, wherein the first and second receiver circuits effectively operate over different ranges of common-mode voltages.

摘要翻译： 在本发明的一个实施例中，接收器具有两个多路复用电路，两个接收器电路和混频器。 多路复用器为接收机电路选择第一和第二输入信号。 每个多路复用器中的传输门中的p型晶体管在其沟道节点处连接（i）在焊盘和多路复用器输出之间，以及（ii）在其栅极节点处接收控制信号。 用于p型晶体管的控制电路实现阈值滤波器，其确保多路复用器输出处的最大电压电平至少低于多路复用器电源电压的阈值。 基于第一和第二输入信号，第一接收器电路产生第一和第二中间信号，第二接收器电路产生第三和第四中间信号。 混频器电路组合中间信号以产生第一和第二输出信号，其中第一和第二接收器电路有效地在不同的共模电压范围上工作。

公开(公告)号：US07230810B1

公开(公告)日：2007-06-12

申请号：US11007954

申请日：2004-12-09

申请人： William B. Andrews ,  Mou C. Lin ,  Larry R. Fenstermaker

发明人： William B. Andrews ,  Mou C. Lin ,  Larry R. Fenstermaker

IPC分类号： H02H9/04

CPC分类号： H01L27/0285

摘要： An integrated circuit having a transistor device and over-voltage protection circuitry. The transistor device is implemented in a technology having a specified operating-voltage range, the transistor device having gate, drain, source, and tub nodes, and the specified operating-voltage range having a specified maximum voltage. The over-voltage protection circuitry is adapted to apply gate and tub voltages to the gate and tub nodes, respectively. If at least one channel voltage applied to at least one of the drain and source nodes exceeds the specified maximum voltage, then the over-voltage protection circuitry controls at least one of the gate voltage and the tub voltage to inhibit one or more adverse effects to the transistor device.

摘要翻译： 具有晶体管器件和过电压保护电路的集成电路。 晶体管器件以具有指定工作电压范围的技术实现，该晶体管器件具有栅极，漏极，源极和源极节点以及具有指定最大电压的规定工作电压范围。 过电压保护电路分别适用于门和电池的电压。 如果施加到至少一个漏极和源极节点的至少一个沟道电压超过规定的最大电压，则过电压保护电路控制栅极电压和电池电压中的至少一个以抑制一个或多个不利影响 晶体管器件。

公开(公告)号：US07215148B1

公开(公告)日：2007-05-08

申请号：US11012548

申请日：2004-12-15

申请人： Phillip L. Johnson ,  William B. Andrews ,  Gregory S. Cartney

发明人： Phillip L. Johnson ,  William B. Andrews ,  Gregory S. Cartney

IPC分类号： H03K19/0175

CPC分类号： H03K19/018585 ,  H03F3/45237 ,  H03F3/4565 ,  H03F2203/45008 ,  H03F2203/45048 ,  H03F2203/45082 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45504 ,  H03F2203/45681

摘要： A buffer for a programmable device has source current circuitry, sink current circuitry, one or more input nodes, one or more output nodes, and switch circuitry. The source current circuitry can be programmably controlled to generate a plurality of different total source currents, and the sink current circuitry can be programmably controlled to generate a plurality of different total sink currents. The one or more input nodes can receive one or more input signals, and the one or more output nodes can present one or more output signals. The switch circuitry can selectively apply at least one of a total source current and a total sink current to the one or more output nodes based on the one or more input signals.

摘要翻译： 用于可编程设备的缓冲器具有源电流电路，灌电流电路，一个或多个输入节点，一个或多个输出节点和开关电路。 可以可编程地控制源极电流电路以产生多个不同的总电源电流，并且可编程地控制吸收电流电路以产生多个不同的总吸收电流。 一个或多个输入节点可以接收一个或多个输入信号，并且一个或多个输出节点可呈现一个或多个输出信号。 基于一个或多个输入信号，开关电路可以选择性地将总源电流和总吸收电流中的至少一个应用于一个或多个输出节点。

公开(公告)号：US06975137B1

公开(公告)日：2005-12-13

申请号：US11055280

申请日：2005-02-10

申请人： John A. Schadt ,  William B. Andrews ,  Zheng Chen ,  Anthony K. Myers ,  David A. Rhein ,  Warren L. Ziegenfus ,  Fulong Zhang ,  Ming Hui Ding ,  Larry R. Fenstermaker

发明人： John A. Schadt ,  William B. Andrews ,  Zheng Chen ,  Anthony K. Myers ,  David A. Rhein ,  Warren L. Ziegenfus ,  Fulong Zhang ,  Ming Hui Ding ,  Larry R. Fenstermaker

IPC分类号： H03K19/177 ,  G06F7/38 ,  G06F17/50 ,  H03K19/00

CPC分类号： H03K19/17736 ,  H03K19/17732 ,  H03K19/17796

摘要： A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.

摘要翻译： 具有可编程逻辑核心，块存储器和I / O电路的可编程逻辑器件（PLD）具有集成到PLD设计中的一个或多个标准单元逻辑块（SLB），以使每个SLB可编程地连接到 任何一个或多个可编程内核，块存储器和/或I / O电路。 基于标准单元的功能块的添加创建了具有增加的总体逻辑密度的PLD，相对于等效的常规PLD（例如FPGA），每个功能的净尺寸，每个功能的净模具尺寸，降低的成本以及功率和性能特性的改善。

公开(公告)号：US06924659B1

公开(公告)日：2005-08-02

申请号：US10628657

申请日：2003-07-28

申请人： William B. Andrews ,  Mou C. Lin

发明人： William B. Andrews ,  Mou C. Lin

IPC分类号： H03K19/177 ,  H04L25/02 ,  H03K17/16

CPC分类号： H03K19/17744 ,  H04L25/0278

摘要： A termination scheme for the I/O circuitry of a programmable device, such as a field-programmable gate array (FPGA), has programmable resistors switchably connected between reference voltages and two of the device's I/O pads and additional programmable resistors switchably connected between the two I/O pads. By appropriately controlling the reference voltages and the resistance levels, a single implementation of the termination scheme can be used to conform to a relatively wide variety of symmetric and non-symmetric complementary and differential signaling applications.

摘要翻译： 用于诸如现场可编程门阵列（FPGA）的可编程器件的I / O电路的端接方案具有可切换地连接在参考电压与器件的I / O焊盘之间的可编程电阻和可切换地连接在 两个I / O焊盘。 通过适当地控制参考电压和电阻电平，终端方案的单一实现可以用于符合相对多种对称和非对称互补和差分信令应用。