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    Low power asynchronous sense amp
    3.
    发明授权
    Low power asynchronous sense amp 有权
    低功率异步感应放大器

    公开(公告)号：US07161862B1

    公开(公告)日：2007-01-09

    申请号：US10996283

    申请日：2004-11-22

    申请人： Mou C. Lin ,  Zheng Chen ,  Larry R. Fenstermaker

    发明人： Mou C. Lin ,  Zheng Chen ,  Larry R. Fenstermaker

    IPC分类号： G11C7/02

    CPC分类号： G11C7/065

    摘要： A memory sense amplifier includes an output and a complement output. The sense amplifier is configured such that a memory cell driving the bit line low enables latching of the bit line low by enabling pull-up of the complement output, and the memory cell driving the complement bit line low enables latching of the complement bit line low by enabling pull-up of the output.

    摘要翻译： 存储读出放大器包括输出和补码输出。 读出放大器被配置为使得驱动位线低的存储单元通过使补码输出上拉而使位线锁存为低电平，并且驱动补码位线的存储单元为低电平使得能够将补码位线锁存 通过启用输出的上拉。

    Bi-directional buffering for memory data lines
    4.
    发明授权
    Bi-directional buffering for memory data lines 有权
    存储器数据线的双向缓冲

    公开(公告)号：US06882555B2

    公开(公告)日：2005-04-19

    申请号：US10464083

    申请日：2003-06-18

    申请人： Larry R. Fenstermaker ,  Zheng Chen ,  Gregory S. Cartney

    发明人： Larry R. Fenstermaker ,  Zheng Chen ,  Gregory S. Cartney

    IPC分类号： G11C7/12 ,  G11C11/419 ,  G11C5/06

    CPC分类号： G11C7/12 ,  G11C11/419

    摘要： Systems and methods are disclosed for implementing configuration memory on a programmable logic device. For example, in accordance with one embodiment of the present invention, bi-directional buffers are implemented between sections of a column of memory. The buffers may provide buffering for data lines extending through the column of memory.

    摘要翻译： 公开了用于在可编程逻辑器件上实现配置存储器的系统和方法。 例如，根据本发明的一个实施例，双向缓冲器在存储器列的部分之间实现。 缓冲器可以为延伸通过存储器列的数据线提供缓冲。

    Low-power configurable delay element
    5.
    发明授权
    Low-power configurable delay element 有权
    低功耗可配置延迟元件

    公开(公告)号：US08461894B1

    公开(公告)日：2013-06-11

    申请号：US13585142

    申请日：2012-08-14

    申请人： Fulong Zhang ,  Zheng Chen ,  Chien Kuang Chen ,  John Schadt

    发明人： Fulong Zhang ,  Zheng Chen ,  Chien Kuang Chen ,  John Schadt

    IPC分类号： H03H11/26

    CPC分类号： H03K5/131

    摘要： In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8×1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4×1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4×1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.

    摘要翻译： 在一个实施例中，可配置延迟元件具有三个阶段。 第一级具有8缓冲器第一延迟链和（8×1）第一多路复用器，其选择八个第一延迟链输出之一。 第二级具有连接的24缓冲器第二延迟链，用于接收第一多路复用器输出并被组织成三个8缓冲子链和选择四个第二延迟链输出之一的（4×1）第二复用器 。 第三级具有96缓冲器第三延迟链，用于接收第二多路复用器输出，并组织成三个32缓冲子链和（4×1）第三复用器，选择四个第三延迟链输出中的一个 作为延迟元件输出信号。 延迟元件控制器通过定时在所有延迟元件缓冲器具有相同状态时进行定时的这些更新来为用于控制延迟元件多路复用器的信号提供无故障更新。 控制器基于延迟元件输出信号的更新时序。

    Low-power, glitch-less, configurable delay element
    6.
    发明授权
    Low-power, glitch-less, configurable delay element 有权
    低功耗，无毛刺，可配置延迟元件

    公开(公告)号：US08248136B1

    公开(公告)日：2012-08-21

    申请号：US13007804

    申请日：2011-01-17

    申请人： Fulong Zhang ,  Zheng Chen ,  Chien Kuang Chen ,  John Schadt

    发明人： Fulong Zhang ,  Zheng Chen ,  Chien Kuang Chen ,  John Schadt

    IPC分类号： H03H11/26

    CPC分类号： H03K5/131

    摘要： In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8×1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4×1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4×1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.

    摘要翻译： 在一个实施例中，可配置延迟元件具有三个阶段。 第一级具有8缓冲器第一延迟链和（8×1）第一多路复用器，其选择八个第一延迟链输出之一。 第二级具有连接的24缓冲器第二延迟链，用于接收第一多路复用器输出并被组织成三个8缓冲子链和选择四个第二延迟链输出之一的（4×1）第二复用器 。 第三级具有96缓冲器第三延迟链，用于接收第二多路复用器输出，并组织成三个32缓冲子链和（4×1）第三复用器，选择四个第三延迟链输出中的一个 作为延迟元件输出信号。 延迟元件控制器通过定时在所有延迟元件缓冲器具有相同状态时进行定时的这些更新来为用于控制延迟元件多路复用器的信号提供无故障更新。 控制器基于延迟元件输出信号的更新时序。

    Pre-configuration programmability of I/O circuitry
    7.
    发明授权
    Pre-configuration programmability of I/O circuitry 有权
    I / O电路的预配置可编程性

    公开(公告)号：US08384428B1

    公开(公告)日：2013-02-26

    申请号：US13006622

    申请日：2011-01-14

    申请人： William B. Andrews ,  Zheng Chen

    发明人： William B. Andrews ,  Zheng Chen

    IPC分类号： H03K19/177 ,  H01L25/00

    CPC分类号： H03K19/017581 ,  H03K19/17744 ,  H03K19/17776

    摘要： In one embodiment of the invention, a programmable logic device, such as an FPGA, has programmable I/O circuits that can be programmed into any one of a number of different operating modes before configuration is completed. As such, the same set of I/O circuits and corresponding I/O pads can be used to configure the device using different configuration interfaces having different interface signaling requirements. Such a device may be able to be implemented using fewer I/O pads than conventional devices that employ a different set of I/O pads for each different type of configuration interface supported by the device.

    摘要翻译： 在本发明的一个实施例中，诸如FPGA的可编程逻辑器件具有可编程I / O电路，其可以在配置完成之前被编程为多个不同操作模式中的任何一个。 因此，可以使用同一组I / O电路和相应的I / O焊盘来配置使用具有不同接口信令要求的不同配置接口的设备。 可以使用比由设备支持的每种不同类型的配置接口采用不同I / O焊盘组的传统设备更少的I / O焊盘来实现这样的器件。

    Brush
    8.
    外观设计
    Brush 有权

    公开(公告)号：USD1019156S1

    公开(公告)日：2024-03-26

    申请号：US29911702

    申请日：2023-09-07

    申请人： Zheng Chen

    设计人： Zheng Chen

    摘要： FIG. 1 is a front, bottom perspective view of a brush, showing my new design;
    FIG. 2 is a rear, top perspective view thereof;
    FIG. 3 is a front elevation view thereof;
    FIG. 4 is a rear elevation view thereof;
    FIG. 5 is a left side elevation view thereof;
    FIG. 6 is a right side elevation view thereof;
    FIG. 7 is a top plan view thereof;
    FIG. 8 is a bottom plan view thereof; and,
    FIG. 9 is an enlarged view of detail “9” identified in FIG. 1.
    The dashed lines in the figures illustrate portions of the brush that form no part of the claimed design. The dash dot dash lines in FIGS. 1 and 9 are for the purpose of illustrating the enlarged view indicators and form no part of the claimed design.

    Context-based search query formation
    9.
    发明授权
    Context-based search query formation 有权

    公开(公告)号：US10984337B2

    公开(公告)日：2021-04-20

    申请号：US13408853

    申请日：2012-02-29

    申请人： Peng Bai ,  Zheng Chen ,  Xuedong David Huang ,  Xiaochuan Ni ,  Jian-Tao Sun ,  Zhimin Zhang

    发明人： Peng Bai ,  Zheng Chen ,  Xuedong David Huang ,  Xiaochuan Ni ,  Jian-Tao Sun ,  Zhimin Zhang

    IPC分类号： G06N20/00 ,  G06F16/332

    摘要： Searching is assisted by recognizing a selection of text from a document as an indication that a user wishes to initiate a search based on the selected text. The user is provided with query suggestions based on the selected text and the query suggestions are ranked based on a context provided by the document. The user may select the text by using a mouse, drawing a circle around the text on a touch screen, or by other input techniques. The query suggestions may be based on query reformulation or query expansion techniques applied to the selected text. Context provided by the document is used by a language model and/or an artificial intelligence system to rank the query suggestions in predicted order of relevance based on the selected text and the context.

    ELECTROMAGNETIC INDUCTION APPARATUS FOR POWER TRANSFER
    10.
    发明申请
    ELECTROMAGNETIC INDUCTION APPARATUS FOR POWER TRANSFER 审中-公开

    公开(公告)号：US20170179728A1

    公开(公告)日：2017-06-22

    申请号：US14971490

    申请日：2015-12-16

    申请人： Keqin Jiang ,  Edward Tao Gao ,  Zheng Chen

    发明人： Keqin Jiang ,  Edward Tao Gao ,  Zheng Chen

    IPC分类号： H02J5/00 ,  H01F38/18

    CPC分类号： H02J5/005 ,  H01F38/14 ,  H01F38/18

    摘要： An electromagnetic induction apparatus for power transfer may include a first portion and a second portion. The first portion has at least one loop of central coil is winded on the central magnetic core, and the second portion has at least one loop of toroidal core winded on the toroidal magnetic core. When the first portion is inserted into the second portion, the toroidal coil is located around an outside periphery of the central coil. Since the central coil and the toroidal coil are mutual inductance on the same magnetic core, the electromagnetic induction efficiency is improved, leading to enhancing more than 50% of the power transmitted rate.