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公开(公告)号：US20070147478A1
公开(公告)日：2007-06-28
申请号：US11486581
申请日：2006-07-14
申请人： Tin Lai , Wilson Wong , Sergey Shumarayev , Simardeep Maangat
发明人： Tin Lai , Wilson Wong , Sergey Shumarayev , Simardeep Maangat
IPC分类号： H04B1/00
CPC分类号： H04B7/005 , H04L25/03006 , H04L25/061
摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies. For low frequency adjustment, user-programmable parameters control the normalized signal amplitude in the signal normalization block and the low frequency adjustment in the equalization block.
摘要翻译： 公开了一种用于调整从通信路径接收的信号的系统和方法。 接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。 接收机可以包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。 在一个实施例中，控制块控制用于高频的均衡块中的频率调整。 对于低频调整，用户可编程参数控制信号归一化块中的归一化信号幅度和均衡块中的低频调整。
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公开(公告)号：US20070041455A1
公开(公告)日：2007-02-22
申请号：US11361192
申请日：2006-02-23
IPC分类号： H04L25/00
CPC分类号： H04L1/243 , H04L25/03878
摘要： Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.
摘要翻译： 用于包含在PLD中的串行数据信号接收器电路包括串联连接并且可单独控制的多个均衡器电路，使得它们可以统一地补偿宽范围的可能的输入信号衰减特性。 其他电路特征可以相对于均衡器电路连接以给予接收机电路其他能力。 例如，这些其他特征可以包括各种类型的环回测试电路，可控终端电阻，可控共模电压以及用于检测输入信号的可控阈值。 接收器电路的控制的各个方面可以是可编程的。
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23.发明授权公开(公告)号：US08194724B1
公开(公告)日：2012-06-05
申请号：US12823783
申请日：2010-06-25
CPC分类号： H04L25/03044 , H04L2025/03356 , H04L2025/03579 , H04L2025/03783
摘要： A programmable logic device is provided with adaptive equalization circuitry that is programmable in one or more respects. Examples of the programmable aspects of the equalization circuitry are (1) the number of taps used, (2) whether integer or fractional spaced taps are used, (3) what starting values are used in the computation of coefficient values, (4) whether satisfactory coefficient values are computed only once or on an on-going basis, (5) whether an error signal is generated using a decision directed algorithm or using a training pattern, (6) what training pattern (if any) is used, and/or (7) the location of the sampling point in the bit period of the signal to be equalized.
摘要翻译： 可编程逻辑器件设置有可在一个或多个方面可编程的自适应均衡电路。 均衡电路的可编程方面的示例是（1）使用的抽头数量，（2）是否使用整数或分数间隔抽头，（3）在系数值的计算中使用什么起始值，（4）是否 （5）是否使用决策导向算法或使用训练模式生成错误信号，（6）使用何种训练模式（如果有的话）和/ 或者（7）要被均衡的信号的位周期内的采样点的位置。
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公开(公告)号：US20070071084A1
公开(公告)日：2007-03-29
申请号：US11238365
申请日：2005-09-28
申请人： Tin Lai , Sergey Shumarayev , Simardeep Maangat , Wilson Wong
发明人： Tin Lai , Sergey Shumarayev , Simardeep Maangat , Wilson Wong
CPC分类号： H03G3/3089 , H04L25/03885
摘要： Equalization circuitry may be used to compensate for the attenuation of a data signal caused by a transmission medium. The control circuitry for the equalization circuitry may generate control inputs for equalization stages that control the amount of gain provided to the data signal. A comparator may determine whether the gain from the equalization circuitry is less than or more than the desired amount of gain. A programmable up/down counter may adjust the counter value based on the output of the comparator. The counter value may be converted into one or more analog voltages using one or more digital-to-analog converters. These analog voltages may be provided to the equalization stages as control inputs. The control circuitry may also include hysteresis circuitry that prevents the counter value from being adjusted when the gain produced by the equalization stages is close to the desired amount of gain.
摘要翻译： 均衡电路可用于补偿由传输介质引起的数据信号的衰减。 用于均衡电路的控制电路可以产生用于控制提供给数据信号的增益量的均衡级的控制输入。 比较器可以确定来自均衡电路的增益是否小于或大于期望的增益量。 可编程上/下计数器可以根据比较器的输出来调整计数器值。 可以使用一个或多个数模转换器将计数器值转换成一个或多个模拟电压。 这些模拟电压可以作为控制输入提供给均衡级。 控制电路还可以包括滞后电路，当由均衡级产生的增益接近期望的增益量时，阻止计数器值被调整。
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公开(公告)号：US08035453B1
公开(公告)日：2011-10-11
申请号：US12577568
申请日：2009-10-12
申请人： Wilson Wong , Allen Chan , Simardeep Maangat , Sergey Shumarayev
发明人： Wilson Wong , Allen Chan , Simardeep Maangat , Sergey Shumarayev
CPC分类号： H03K3/0322 , H03L7/0995 , H03L2207/06
摘要： An oscillator circuit includes differential variable delay circuits coupled together to form a ring oscillator. Each of the differential variable delay circuits has first and second inputs and first, second, third, and fourth transistors. A constant supply voltage is provided to sources of the first and the second transistors in each of the differential variable delay circuits. A variable supply voltage is provided to sources of the third and the fourth transistors in each of the differential variable delay circuits. Gates of the first and the third transistors are coupled to the first input. Gates of the second and the fourth transistors are coupled to the second input. The oscillator circuit generates a periodic output signal having a frequency that varies based on changes in the variable supply voltage.
摘要翻译： 振荡器电路包括耦合在一起以形成环形振荡器的差分可变延迟电路。 每个差分可变延迟电路具有第一和第二输入以及第一，第二，第三和第四晶体管。 在每个差分可变延迟电路中，向第一和第二晶体管的源极提供恒定的电源电压。 可变电源电压被提供给每个差分可变延迟电路中的第三和第四晶体管的源极。 第一和第三晶体管的栅极耦合到第一输入端。 第二和第四晶体管的栅极耦合到第二输入端。 振荡器电路产生具有基于可变电源电压的变化而变化的频率的周期性输出信号。
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公开(公告)号：US20060220681A1
公开(公告)日：2006-10-05
申请号：US11098832
申请日：2005-04-04
申请人： Wilson Wong , Tim Hoang , Sergey Shumarayev , Rakesh Patel , Simardeep Maangat
发明人： Wilson Wong , Tim Hoang , Sergey Shumarayev , Rakesh Patel , Simardeep Maangat
IPC分类号： H03K19/094
CPC分类号： H03K19/017545
摘要： Circuitry and methods are provided for an LVDS-like transmitter that may be able to DC couple to a receiver having a CML termination scheme. Replacing the common mode voltage source of an LVDS transmitter with a resistive pulldown to ground may allow the transmitter to interface in a DC coupled fashion with a CML receiver. Further, the resistive pulldown may be programmable. This LVDS-like transmitter may be able to support a wider customer base by allowing it to DC couple to a wider range of termination voltage levels, such as CML termination voltage levels.
摘要翻译： 为能够将DC耦合到具有CML终止方案的接收机的类似LVDS的发射机提供电路和方法。 将具有电阻下拉到地的LVDS发射机的共模电压源替换可允许发射机以直流耦合方式与CML接收器接口。 此外，电阻下拉可以是可编程的。 这种类似LVDS的发射机可能能够通过允许其将DC耦合到更广泛的终止电压电平范围（例如CML终止电压电平）来支持更广泛的客户群。
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公开(公告)号：US08049532B1
公开(公告)日：2011-11-01
申请号：US12823596
申请日：2010-06-25
申请人： Simardeep Maangat , Vinh Van Ho , Tim Tri Hoang
发明人： Simardeep Maangat , Vinh Van Ho , Tim Tri Hoang
IPC分类号： H03K19/0175 , H03L5/00
CPC分类号： H03L7/085 , H03K19/017509 , H03L7/087
摘要： A level shifting circuit with a thin gate transistor connected to the input of the output stage is presented. The level shifting circuit has an input stage that receives an input that is at first voltage. A transistor with a thin gate oxide has one terminal connected to the input stage and another terminal coupled to an input of the output stage. The output stage of the level shifting circuit is implemented with thick gate oxide transistors.
摘要翻译： 提出了一种具有连接到输出级的输入端的薄栅极晶体管的电平移动电路。 电平移位电路具有接收处于第一电压的输入的输入级。 具有薄栅极氧化物的晶体管具有连接到输入级的一个端子和耦合到输出级的输入的另一个端子。 电平移位电路的输出级由厚栅极氧化物晶体管实现。
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公开(公告)号：US07638990B1
公开(公告)日：2009-12-29
申请号：US11754295
申请日：2007-05-27
CPC分类号： G05F1/56
摘要： A power management system on an integrated circuit can include a first switch and a second switch. A regulator circuit provides current from a first supply voltage to a circuit block when the first switch is closed. The second switch provides current from a second supply voltage to the circuit block when the second switch is closed.
摘要翻译： 集成电路上的电源管理系统可以包括第一开关和第二开关。 当第一开关闭合时，调节器电路将电流从第一电源电压提供给电路块。 当第二开关闭合时，第二开关将电流从第二电源电压提供给电路块。
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公开(公告)号：US08933751B1
公开(公告)日：2015-01-13
申请号：US13475678
申请日：2012-05-18
申请人： Wilson Wong , Weiqi Ding , Shuxian Chen , Simardeep Maangat , Albert Ratnakumar
发明人： Wilson Wong , Weiqi Ding , Shuxian Chen , Simardeep Maangat , Albert Ratnakumar
摘要： A first trimming capacitor having a first terminal and a second terminal is coupled in parallel between a first terminal and a second terminal of a first capacitor. The first trimming capacitor comprises a first plurality of switched capacitors having different capacitances coupled in parallel. Each of the switched capacitors comprises a switch capacitor and a switch coupled in series. In an illustrative application the first capacitor and the first trimming capacitor are coupled between an output terminal of an operational amplifier (op-amp) and an inverting input terminal of the op-amp. A second capacitor and a second trimming capacitor similar to the first capacitor and the first trimming capacitor are coupled between an input and the inverting input terminal of the op-amp.
摘要翻译： 具有第一端子和第二端子的第一微调电容器并联耦合在第一电容器的第一端子和第二端子之间。 第一微调电容器包括具有并联耦合的不同电容的第一多个开关电容器。 每个开关电容器包括开关电容器和串联耦合的开关。 在说明性应用中，第一电容器和第一微调电容器耦合在运算放大器（运算放大器）的输出端和运算放大器的反相输入端之间。 类似于第一电容器和第一微调电容器的第二电容器和第二微调电容器耦合在运算放大器的输入端和反相输入端子之间。
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公开(公告)号：US07702011B2
公开(公告)日：2010-04-20
申请号：US11361192
申请日：2006-02-23
IPC分类号： H03H7/30
CPC分类号： H04L1/243 , H04L25/03878
摘要： Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.
摘要翻译： 用于包含在PLD中的串行数据信号接收器电路包括串联连接并且可单独控制的多个均衡器电路，使得它们可以统一地补偿宽范围的可能的输入信号衰减特性。 其他电路特征可以相对于均衡器电路连接以给予接收机电路其他能力。 例如，这些其他特征可以包括各种类型的环回测试电路，可控终端电阻，可控共模电压以及用于检测输入信号的可控阈值。 接收器电路的控制的各个方面可以是可编程的。
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