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公开(公告)号：US08933751B1
公开(公告)日：2015-01-13
申请号：US13475678
申请日：2012-05-18
申请人： Wilson Wong , Weiqi Ding , Shuxian Chen , Simardeep Maangat , Albert Ratnakumar
发明人： Wilson Wong , Weiqi Ding , Shuxian Chen , Simardeep Maangat , Albert Ratnakumar
摘要： A first trimming capacitor having a first terminal and a second terminal is coupled in parallel between a first terminal and a second terminal of a first capacitor. The first trimming capacitor comprises a first plurality of switched capacitors having different capacitances coupled in parallel. Each of the switched capacitors comprises a switch capacitor and a switch coupled in series. In an illustrative application the first capacitor and the first trimming capacitor are coupled between an output terminal of an operational amplifier (op-amp) and an inverting input terminal of the op-amp. A second capacitor and a second trimming capacitor similar to the first capacitor and the first trimming capacitor are coupled between an input and the inverting input terminal of the op-amp.
摘要翻译： 具有第一端子和第二端子的第一微调电容器并联耦合在第一电容器的第一端子和第二端子之间。 第一微调电容器包括具有并联耦合的不同电容的第一多个开关电容器。 每个开关电容器包括开关电容器和串联耦合的开关。 在说明性应用中，第一电容器和第一微调电容器耦合在运算放大器（运算放大器）的输出端和运算放大器的反相输入端之间。 类似于第一电容器和第一微调电容器的第二电容器和第二微调电容器耦合在运算放大器的输入端和反相输入端子之间。
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公开(公告)号：US08264214B1
公开(公告)日：2012-09-11
申请号：US13051648
申请日：2011-03-18
申请人： Albert Ratnakumar , Qi Xiang , Simardeep Maangat , Jun Liu
发明人： Albert Ratnakumar , Qi Xiang , Simardeep Maangat , Jun Liu
IPC分类号： G05F3/16
CPC分类号： G05F3/30
摘要： A low-voltage reference circuit may have a pair of semiconductor devices. Each semiconductor device may have an n-type semiconductor region, an n+ region in the n-type semiconductor region, a metal gate, and a gate insulator interposed between the metal gate and the n-type semiconductor region through which carriers tunnel. The metal gate may have a work function matching that of p-type polysilicon. The gate insulator may have a thickness of less than about 25 angstroms. The metal gate may form a first terminal for the semiconductor device and the n+ region and n-type semiconductor region may form a second terminal for the semiconductor device. The second terminals may be coupled to ground. A biasing circuit may use the first terminals to supply different currents to the semiconductor devices and may provide a corresponding reference output voltage at a value that is less than one volt.
摘要翻译： 低压参考电路可以具有一对半导体器件。 每个半导体器件可以具有n型半导体区域，n型半导体区域中的n +区域，金属栅极和介于金属栅极和n型半导体区域之间的栅极绝缘体，载流子穿过该栅极绝缘体。 金属栅极可以具有与p型多晶硅相匹配的功函数。 栅极绝缘体可以具有小于约25埃的厚度。 金属栅极可以形成用于半导体器件的第一端子，并且n +区域和n型半导体区域可以形成用于半导体器件的第二端子。 第二端子可以接地。 偏置电路可以使用第一端子来向半导体器件提供不同的电流，并且可以将相应的参考输出电压提供在小于1伏的值。
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公开(公告)号：US20120235662A1
公开(公告)日：2012-09-20
申请号：US13051648
申请日：2011-03-18
申请人： Albert Ratnakumar , Qi Xiang , Simardeep Maangat , Jun Liu
发明人： Albert Ratnakumar , Qi Xiang , Simardeep Maangat , Jun Liu
IPC分类号： G05F3/02
CPC分类号： G05F3/30
摘要： A low-voltage reference circuit may have a pair of semiconductor devices. Each semiconductor device may have an n-type semiconductor region, an n+ region in the n-type semiconductor region, a metal gate, and a gate insulator interposed between the metal gate and the n-type semiconductor region through which carriers tunnel. The metal gate may have a work function matching that of p-type polysilicon. The gate insulator may have a thickness of less than about 25 angstroms. The metal gate may form a first terminal for the semiconductor device and the n+ region and n-type semiconductor region may form a second terminal for the semiconductor device. The second terminals may be coupled to ground. A biasing circuit may use the first terminals to supply different currents to the semiconductor devices and may provide a corresponding reference output voltage at a value that is less than one volt.
摘要翻译： 低压参考电路可以具有一对半导体器件。 每个半导体器件可以具有n型半导体区域，n型半导体区域中的n +区域，金属栅极和介于金属栅极和n型半导体区域之间的栅极绝缘体，载流子穿过该栅极绝缘体。 金属栅极可以具有与p型多晶硅相匹配的功函数。 栅极绝缘体可以具有小于约25埃的厚度。 金属栅极可以形成用于半导体器件的第一端子，并且n +区域和n型半导体区域可以形成用于半导体器件的第二端子。 第二端子可以接地。 偏置电路可以使用第一端子来向半导体器件提供不同的电流，并且可以将相应的参考输出电压提供在小于1伏的值。
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公开(公告)号：US08120429B1
公开(公告)日：2012-02-21
申请号：US12787722
申请日：2010-05-26
申请人： Tim Tri Hoang , Wilson Wong , Kazi Asaduzzaman , Simardeep Maangat , Sergey Shumarayev , Rakesh H. Patel
发明人： Tim Tri Hoang , Wilson Wong , Kazi Asaduzzaman , Simardeep Maangat , Sergey Shumarayev , Rakesh H. Patel
CPC分类号： H03L7/0995 , H03K3/0322 , H03K3/35613 , H03K2005/00228 , H03K2005/00234
摘要： Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.
摘要翻译： 提供了用于产生具有相对较高带宽和相对较低相位噪声的时钟信号的方法和装置。 本发明的电路可以包括串联耦合在相对高电压的信号和相对低电压的源之间的一对晶体管，其中相对高电压的信号的电压可以根据可变控制信号的电压而变化。 一对晶体管中的一个的栅极可以耦合到输入时钟信号，并且该对晶体管之间的输出节点可以耦合到输出时钟信号。 电路还可以包括第三晶体管，其漏极和源极耦合到输出时钟信号，并且其栅极可以耦合到齿轮输入信号。 该电路可以有利地在至少两个不同的齿轮下运行，每个齿轮具有不同的带宽和相位噪声特性。
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5.发明授权Signal amplitude detection circuitry without pattern dependencies for high-speed serial links 有权信号幅度检测电路，无高速串行链路的模式相关性公开(公告)号：US07576570B1
公开(公告)日：2009-08-18
申请号：US11508607
申请日：2006-08-22
IPC分类号： H03K5/153
摘要： Precision amplitude detection circuitry without pattern dependencies is provided that includes rectifier circuitry to output a rectified voltage signal and delay circuitry to send one or more delayed or phase-shifted versions of a differential signal input to the rectifier circuitry. The delayed versions of the differential signal input may be delayed in order to reduce or eliminate the dips in the input seen by the rectifier. This may help correct for low rectified voltage levels. The signal amplitude detection circuitry of the present invention may be incorporated on the input pin of any programmable logic resource and may be included in communication circuitry of a PLD. The precision amplitude detection circuitry may operate in the Gbps (gigabit per second) range.
摘要翻译： 提供了没有图形相关性的精密幅度检测电路，其包括整流电路，用于输出整流电压信号和延迟电路，以将一个或多个差分信号输入的延迟或相移版本发送到整流器电路。 可以延迟差分信号输入的延迟版本，以便减少或消除由整流器看到的输入中的下降。 这可能有助于校正低整流电压电平。 本发明的信号幅度检测电路可以结合在任何可编程逻辑资源的输入引脚上，并且可以被包括在PLD的通信电路中。 精度幅度检测电路可以以Gbps（千兆位/秒）范围工作。
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6.发明授权Increased sensitivity and reduced offset variation in high data rate HSSI receiver 有权在高数据速率HSSI接收机中增加灵敏度和减少偏移变化公开(公告)号：US07777526B2
公开(公告)日：2010-08-17
申请号：US12134777
申请日：2008-06-06
IPC分类号： H03K19/094
CPC分类号： H03K19/018514 , H03F3/45197 , H03F2203/45494 , H03F2203/45686
摘要： Signal offset variation caused by transistor variation/mismatch in integrated circuits may be reduced. In one embodiment, a buffer circuit has variable-valued circuit elements. Offset variation measurements are made and the variable-valued circuit elements are calibrated to reduce the measured offset variation. In another embodiment, each amplifying stage of a multi-stage buffer provides variable gain. The total DC gain of the cascade is distributed unevenly across the stages, with more DC gain being provided by amplifier stages at the beginning of the cascade than at the end. An additional pre-amplifier stage can also be provided at the beginning of the cascade.
摘要翻译： 集成电路中晶体管变化/失配引起的信号偏移变化可能会降低。 在一个实施例中，缓冲电路具有可变值电路元件。 进行偏移变化测量，并校准可变值电路元件以减少测量的偏移变化。 在另一个实施例中，多级缓冲器的每个放大级提供可变增益。 级联的总直流增益不均匀地分布在整个级中，在级联开始时比放大器级提供更多的直流增益。 在级联开始时也可以提供一个额外的前级放大器级。
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公开(公告)号：US07697600B2
公开(公告)日：2010-04-13
申请号：US11182658
申请日：2005-07-14
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H04B3/04 , H04L25/03019
摘要： Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry may be provided to compensate for attenuation caused by the transmission media. Equalization circuitry may include multiple stages arranged in series to allow the frequency responses of the stages to aggregate together. Each stage may be programmable to insert a zero, which causes the frequency response of the stage to increase in magnitude by 20 dB/decade. The frequency location of the zero may also be programmable to allow each stage to contribute a certain amount of gain for a specific frequency. Each stage may also be programmable to determine the location of poles for reduction of high frequency noise and cross-talk cancellation.
摘要翻译： 通过传输介质传输的数据信号遭受由传输介质引起的衰减。 可以提供均衡电路以补偿由传输介质引起的衰减。 均衡电路可以包括串联布置的多个级，以允许级的频率响应聚合在一起。 每个级可以是可编程的，以插入一个零，这使得该级的频率响应在幅度上增加20dB /十倍。 零的频率位置也可以是可编程的，以允许每个级对特定频率贡献一定量的增益。 每个阶段也可以被编程以确定用于降低高频噪声和串扰取消的极点的位置。
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公开(公告)号：US20070014344A1
公开(公告)日：2007-01-18
申请号：US11182658
申请日：2005-07-14
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H04B3/04 , H04L25/03019
摘要： Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry may be provided to compensate for attenuation caused by the transmission media. Equalization circuitry may include multiple stages arranged in series to allow the frequency responses of the stages to aggregate together. Each stage may be programmable to insert a zero, which causes the frequency response of the stage to increase in magnitude by 20 dB/decade. The frequency location of the zero may also be programmable to allow each stage to contribute a certain amount of gain for a specific frequency. Each stage may also be programmable to determine the location of poles for reduction of high frequency noise and cross-talk cancellation.
摘要翻译： 通过传输介质传输的数据信号遭受由传输介质引起的衰减。 可以提供均衡电路以补偿由传输介质引起的衰减。 均衡电路可以包括串联布置的多个级，以允许级的频率响应聚合在一起。 每个级可以是可编程的，以插入一个零，这使得该级的频率响应在幅度上增加20dB /十倍。 零的频率位置也可以是可编程的，以允许每个级对特定频率贡献一定量的增益。 每个阶段也可以被编程以确定用于降低高频噪声和串扰取消的极点的位置。
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9.发明授权公开(公告)号：US07920621B2
公开(公告)日：2011-04-05
申请号：US11522284
申请日：2006-09-14
申请人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
IPC分类号： H03H7/30
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译： 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。
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10.发明授权公开(公告)号：US07773668B1
公开(公告)日：2010-08-10
申请号：US10762864
申请日：2004-01-21
CPC分类号： H04L25/03044 , H04L2025/03356 , H04L2025/03579 , H04L2025/03783
摘要： A programmable logic device is provided with adaptive equalization circuitry that is programmable in one or more respects. Examples of the programmable aspects of the equalization circuitry are (1) the number of taps used, (2) whether integer or fractional spaced taps are used, (3) what starting values are used in the computation of coefficient values, (4) whether satisfactory coefficient values are computed only once or on an on-going basis, (5) whether an error signal is generated using a decision directed algorithm or using a training pattern, (6) what training pattern (if any) is used, and/or (7) the location of the sampling point in the bit period of the signal to be equalized.
摘要翻译： 可编程逻辑器件设置有可在一个或多个方面可编程的自适应均衡电路。 均衡电路的可编程方面的示例是（1）使用的抽头数量，（2）是否使用整数或分数间隔抽头，（3）在系数值的计算中使用什么起始值，（4）是否 （5）是否使用决策导向算法或使用训练模式生成错误信号，（6）使用何种训练模式（如果有的话）和/ 或者（7）要被均衡的信号的位周期内的采样点的位置。
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