公开(公告)号：US08530976B1

公开(公告)日：2013-09-10

申请号：US13113896

申请日：2011-05-23

申请人： Albert Ratnakumar ,  Qi Xiang ,  Jun Liu

发明人： Albert Ratnakumar ,  Qi Xiang ,  Jun Liu

IPC分类号： H01L21/70

CPC分类号： H01L29/7833 ,  H01L21/823842 ,  H01L27/1104

摘要： Integrated circuits may be provided that include memory elements that produce output control signals and corresponding programmable logic circuitry that receives the output control signals from the memory elements. The memory elements may include bistable storage elements formed from circuits such as cross-coupled inverters. The inverters may include n-channel metal-oxide-semiconductor transistors with p-metal gate conductors and n-channel metal-oxide-semiconductor transistors with p-metal gate conductors. These gate conductor assignments are the reverse of the gate conductor assignments used in the n-channel and p-channel transistors in other circuitry such as the programmable logic circuitry. The reversed gate conductor assignments increase the threshold voltages of the transistors in the memory elements to improve reliability in scenarios in which the memory elements are overdriving pass transistors in the programmable logic circuitry.

摘要翻译： 可以提供集成电路，其包括产生输出控制信号的存储器元件和从存储器元件接收输出控制信号的相应的可编程逻辑电路。 存储器元件可以包括由诸如交叉耦合的反相器的电路形成的双稳态存储元件。 反相器可以包括具有p金属栅极导体的n沟道金属氧化物半导体晶体管和具有p型金属栅极导体的n沟道金属氧化物半导体晶体管。 这些栅极导体分配与在诸如可编程逻辑电路的其它电路中的n沟道和p沟道晶体管中使用的栅极导体分配相反。 反向栅极导体分配增加存储器元件中的晶体管的阈值电压，以提高存储元件过驱动可编程逻辑电路中的通过晶体管的情况下的可靠性。

公开(公告)号：US08264214B1

公开(公告)日：2012-09-11

申请号：US13051648

申请日：2011-03-18

申请人： Albert Ratnakumar ,  Qi Xiang ,  Simardeep Maangat ,  Jun Liu

发明人： Albert Ratnakumar ,  Qi Xiang ,  Simardeep Maangat ,  Jun Liu

IPC分类号： G05F3/16

CPC分类号： G05F3/30

摘要： A low-voltage reference circuit may have a pair of semiconductor devices. Each semiconductor device may have an n-type semiconductor region, an n+ region in the n-type semiconductor region, a metal gate, and a gate insulator interposed between the metal gate and the n-type semiconductor region through which carriers tunnel. The metal gate may have a work function matching that of p-type polysilicon. The gate insulator may have a thickness of less than about 25 angstroms. The metal gate may form a first terminal for the semiconductor device and the n+ region and n-type semiconductor region may form a second terminal for the semiconductor device. The second terminals may be coupled to ground. A biasing circuit may use the first terminals to supply different currents to the semiconductor devices and may provide a corresponding reference output voltage at a value that is less than one volt.

摘要翻译： 低压参考电路可以具有一对半导体器件。 每个半导体器件可以具有n型半导体区域，n型半导体区域中的n +区域，金属栅极和介于金属栅极和n型半导体区域之间的栅极绝缘体，载流子穿过该栅极绝缘体。 金属栅极可以具有与p型多晶硅相匹配的功函数。 栅极绝缘体可以具有小于约25埃的厚度。 金属栅极可以形成用于半导体器件的第一端子，并且n +区域和n型半导体区域可以形成用于半导体器件的第二端子。 第二端子可以接地。 偏置电路可以使用第一端子来向半导体器件提供不同的电流，并且可以将相应的参考输出电压提供在小于1伏的值。

公开(公告)号：US07952423B2

公开(公告)日：2011-05-31

申请号：US12241706

申请日：2008-09-30

申请人： Qi Xiang ,  Albert Ratnakumar ,  Jeffrey Xiaoqi Tung ,  Weiqi Ding

发明人： Qi Xiang ,  Albert Ratnakumar ,  Jeffrey Xiaoqi Tung ,  Weiqi Ding

IPC分类号： G05F1/10

CPC分类号： G05F3/205 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.

摘要翻译： 提出了使用正向偏置电路设计和改进的混合信号处理来提高模拟电路性能的方法。 定义了包括多个NMOS和PMOS晶体管的电路。 NMOS晶体管的主体端子耦合到第一电压源，并且PMOS晶体管的主体端子耦合第二电压源。 通过将第一电压源施加到每个选定的NMOS晶体管的主体端子并将第二电压源施加到每个选择的PMOS晶体管的主体端子来选择性地偏置电路中的晶体管。 在一个实施例中，第一电压源和第二电压源是可修改的，以向晶体管的主体端子提供正向和反向偏置。

公开(公告)号：US09627138B1

公开(公告)日：2017-04-18

申请号：US13350679

申请日：2012-01-13

申请人： Shuxian Chen ,  Albert Ratnakumar ,  Yan Cui ,  Jeffrey T. Watt

发明人： Shuxian Chen ,  Albert Ratnakumar ,  Yan Cui ,  Jeffrey T. Watt

IPC分类号： H01G4/005 ,  H01G4/30 ,  H01G4/232

CPC分类号： H01G4/30 ,  H01G4/005 ,  H01G4/232

摘要： Apparatus for integrated capacitors and associated methods are disclosed. In one embodiment, an integrated capacitor includes a first plurality of metal members that are fabricated using a first plurality of metal layers, and are oriented in a first orientation. The integrated capacitor also includes a second plurality of metal members that are fabricated using a second plurality of metal layers. The second plurality of metal members are oriented transverse to the first orientation. The integrated capacitor further includes a third plurality of metal members, which are fabricated using a third plurality of metal layers, and are oriented in the first orientation.

公开(公告)号：US09196749B1

公开(公告)日：2015-11-24

申请号：US13341310

申请日：2011-12-30

申请人： Charu Sardana ,  Albert Ratnakumar ,  Qi Xiang ,  Bradley Jensen

发明人： Charu Sardana ,  Albert Ratnakumar ,  Qi Xiang ,  Bradley Jensen

IPC分类号： H01L29/66 ,  H01L29/788 ,  H01L27/112

CPC分类号： H01L27/112 ,  H01L27/11206 ,  H01L29/66 ,  H01L29/7881

摘要： A programmable device with a metal oxide semiconductor field effect transistor (MOSFET) surrounded by a programmable substrate region is described. The MOSFET has a source and drain region separated by a channel region with an insulating region and gate disposed above the channel region. A junction disposed within the substrate region controls the programmable substrate region. Biasing the junction depletes the substrate region, which isolates the body of the MOSFET from a secondary well. When the junction is left unbiased, the body of the MOSFET is electrically coupled to the secondary well.

摘要翻译： 描述了由可编程衬底区域包围的具有金属氧化物半导体场效应晶体管（MOSFET）的可编程器件。 MOSFET具有由具有绝缘区域的沟道区域和设置在沟道区域上方的栅极分隔的源极和漏极区域。 设置在衬底区域内的接合部控制可编程衬底区域。 偏置连接点会耗尽衬底区域，从而将MOSFET的主体与次级阱隔离。 当结点保持不偏差时，MOSFET的主体电耦合到次级阱。

公开(公告)号：US08933751B1

公开(公告)日：2015-01-13

申请号：US13475678

申请日：2012-05-18

申请人： Wilson Wong ,  Weiqi Ding ,  Shuxian Chen ,  Simardeep Maangat ,  Albert Ratnakumar

发明人： Wilson Wong ,  Weiqi Ding ,  Shuxian Chen ,  Simardeep Maangat ,  Albert Ratnakumar

IPC分类号： H03F3/45 ,  H01G4/40 ,  H03F1/56

CPC分类号： H01G4/40 ,  H01G17/00 ,  H03F1/56

摘要： A first trimming capacitor having a first terminal and a second terminal is coupled in parallel between a first terminal and a second terminal of a first capacitor. The first trimming capacitor comprises a first plurality of switched capacitors having different capacitances coupled in parallel. Each of the switched capacitors comprises a switch capacitor and a switch coupled in series. In an illustrative application the first capacitor and the first trimming capacitor are coupled between an output terminal of an operational amplifier (op-amp) and an inverting input terminal of the op-amp. A second capacitor and a second trimming capacitor similar to the first capacitor and the first trimming capacitor are coupled between an input and the inverting input terminal of the op-amp.

摘要翻译： 具有第一端子和第二端子的第一微调电容器并联耦合在第一电容器的第一端子和第二端子之间。 第一微调电容器包括具有并联耦合的不同电容的第一多个开关电容器。 每个开关电容器包括开关电容器和串联耦合的开关。 在说明性应用中，第一电容器和第一微调电容器耦合在运算放大器（运算放大器）的输出端和运算放大器的反相输入端之间。 类似于第一电容器和第一微调电容器的第二电容器和第二微调电容器耦合在运算放大器的输入端和反相输入端子之间。

公开(公告)号：US20120235662A1

公开(公告)日：2012-09-20

申请号：US13051648

申请日：2011-03-18

申请人： Albert Ratnakumar ,  Qi Xiang ,  Simardeep Maangat ,  Jun Liu

发明人： Albert Ratnakumar ,  Qi Xiang ,  Simardeep Maangat ,  Jun Liu

IPC分类号： G05F3/02

CPC分类号： G05F3/30

摘要： A low-voltage reference circuit may have a pair of semiconductor devices. Each semiconductor device may have an n-type semiconductor region, an n+ region in the n-type semiconductor region, a metal gate, and a gate insulator interposed between the metal gate and the n-type semiconductor region through which carriers tunnel. The metal gate may have a work function matching that of p-type polysilicon. The gate insulator may have a thickness of less than about 25 angstroms. The metal gate may form a first terminal for the semiconductor device and the n+ region and n-type semiconductor region may form a second terminal for the semiconductor device. The second terminals may be coupled to ground. A biasing circuit may use the first terminals to supply different currents to the semiconductor devices and may provide a corresponding reference output voltage at a value that is less than one volt.

摘要翻译： 低压参考电路可以具有一对半导体器件。 每个半导体器件可以具有n型半导体区域，n型半导体区域中的n +区域，金属栅极和介于金属栅极和n型半导体区域之间的栅极绝缘体，载流子穿过该栅极绝缘体。 金属栅极可以具有与p型多晶硅相匹配的功函数。 栅极绝缘体可以具有小于约25埃的厚度。 金属栅极可以形成用于半导体器件的第一端子，并且n +区域和n型半导体区域可以形成用于半导体器件的第二端子。 第二端子可以接地。 偏置电路可以使用第一端子来向半导体器件提供不同的电流，并且可以将相应的参考输出电压提供在小于1伏的值。

公开(公告)号：US08242581B1

公开(公告)日：2012-08-14

申请号：US12324793

申请日：2008-11-26

申请人： Albert Ratnakumar ,  Wilson Wong ,  Jun Liu ,  Qi Xiang ,  Jeffrey Xiaoqi Tung

发明人： Albert Ratnakumar ,  Wilson Wong ,  Jun Liu ,  Qi Xiang ,  Jeffrey Xiaoqi Tung

IPC分类号： H01L29/93

CPC分类号： H01L29/94 ,  H01L29/4983 ,  H01L29/93

摘要： Mixed gate varactors are provided. The mixed gate varactors may include a semiconductor region of a given doping type. A first terminal for the varactor may be formed from a gate structure on the semiconductor region. A second terminal for the varactor may be formed from a heavily doped region in the semiconductor region that has the same doping type as the given doping type. A third terminal for the varactor may be formed from a heavily doped region in the semiconductor region that has a different doping type than the given doping type. The gate structure may include multiple gate conductors on a gate insulator. The gate insulator may be a high-K dielectric. The gate conductors may be metals or other materials that have different work functions. A conductive layer such as a layer of polysilicon may electrically connect the first and second gate conductors.

摘要翻译： 提供混合栅极变容二极管。 混合栅极变容二极管可以包括给定掺杂型的半导体区域。 用于变容二极管的第一端可以由半导体区域上的栅极结构形成。 用于变容二极管的第二端子可以由具有与给定掺杂类型相同的掺杂类型的半导体区域中的重掺杂区域形成。 用于变容二极管的第三端子可以由具有与给定掺杂类型不同的掺杂类型的半导体区域中的重掺杂区域形成。 栅极结构可以包括栅极绝缘体上的多个栅极导体。 栅极绝缘体可以是高K电介质。 栅极导体可以是具有不同功函数的金属或其它材料。 诸如多晶硅层的导电层可电连接第一和第二栅极导体。

公开(公告)号：US08116130B1

公开(公告)日：2012-02-14

申请号：US12551796

申请日：2009-09-01

申请人： Albert Ratnakumar ,  Shuang Xie ,  Cheng-Hsiung Huang ,  Yow-Juang Bill Liu

发明人： Albert Ratnakumar ,  Shuang Xie ,  Cheng-Hsiung Huang ,  Yow-Juang Bill Liu

IPC分类号： G11C11/34

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/11206 ,  H01L27/11286 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

摘要： Nonvolatile memory element circuitry is provided that is based on metal-oxide-semiconductor transistor structures. A nonvolatile memory element may be based on a metal-oxide-semiconductor transistor structure that has a gate, a drain, a source, and a body. During programming operations, control circuitry floats the body while applying a positive voltage to the drain and a negative voltage to the source. This causes the drain and source, which serve as the collector and emitter in a parasitic bipolar transistor, to break down. The drain-to-source (collector-to-emitter) breakdown causes sufficient current to flow through the source to alter the source electrode and thereby increase the resistance of the source significantly. During sensing operations, control circuitry may apply a voltage across the drain and source while grounding the body to determine whether the memory element has been programmed.

摘要翻译： 提供了基于金属氧化物半导体晶体管结构的非易失性存储元件电路。 非易失性存储元件可以基于具有栅极，漏极，源极和主体的金属氧化物半导体晶体管结构。 在编程操作期间，控制电路漂浮身体，同时向漏极施加正电压，并向源提供负电压。 这导致用作寄生双极晶体管中的集电极和发射极的漏极和源极分解。 漏极到源极（集电极到发射极）击穿导致足够的电流流过源极以改变源电极，从而显着增加源极的电阻。 在感测操作期间，控制电路可以在接地主体时在漏极和源极之间施加电压，以确定存储器元件是否已被编程。

公开(公告)号：US08482963B1

公开(公告)日：2013-07-09

申请号：US12629831

申请日：2009-12-02

申请人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

发明人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

摘要翻译： 不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。 也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。 可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。 两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。 两个晶体管的栅极也连接在一起。 两个晶体管可以具有不同的阈值电压。 位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。 堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。 不对称晶体管也可用于存储器单元中以减少泄漏。