公开(公告)号：US11296707B1

公开(公告)日：2022-04-05

申请号：US17196574

申请日：2021-03-09

Applicant: Xilinx, Inc.

Inventor： Javier Cabezas Rodriguez ,  Juan J. Noguera Serra ,  David Clarke ,  Sneha Bhalchandra Date ,  Tim Tuan ,  Peter McColgan ,  Jan Langer ,  Baris Ozgul

IPC: H03K19/1776 ,  H03K19/17704 ,  H03K19/17768 ,  H03K19/17758 ,  H03K19/17796

Abstract: An integrated circuit can include a data processing engine (DPE) array having a plurality of tiles. The plurality of tiles can include a plurality of DPE tiles, wherein each DPE tile includes a stream switch, a core configured to perform operations, and a memory module. The plurality of tiles can include a plurality of memory tiles, wherein each memory tile includes a stream switch, a direct memory access (DMA) engine, and a random-access memory. The DMA engine of each memory tile may be configured to access the random-access memory within the same memory tile and the random-access memory of at least one other memory tile. Selected ones of the plurality of DPE tiles may be configured to access selected ones of the plurality of memory tiles via the stream switches.

公开(公告)号：US10747531B1

公开(公告)日：2020-08-18

申请号：US15944315

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Jan Langer ,  Baris Ozgul ,  Juan J. Noguera Serra ,  Goran HK Bilski ,  Tim Tuan

IPC: G06F9/302 ,  G06F7/57 ,  G06F15/76 ,  G06F9/30 ,  G06F9/38 ,  G06F7/499 ,  G06F15/80

Abstract: An example core for a data processing engine (DPE) includes a register file, a processor, coupled to the register file. The processor includes a multiply-accumulate (MAC) circuit, and permute circuitry coupled between the register file and the MAC circuit, the permute circuitry configured to concatenate at least one pair of outputs of the register file to provide at least one input to the MAC circuit. The core further includes an instruction decoder, coupled to the processor, configured to decode a very large instruction word (VLIW) to set a plurality of parameters of the processor, the plurality of parameters including first parameters of the permute circuitry and second parameters of the MAC circuit.

公开(公告)号：US20200076660A1

公开(公告)日：2020-03-05

申请号：US16117605

申请日：2018-08-30

Applicant: Xilinx, Inc.

Inventor： Kaushik Barman ,  Parag Dighe ,  Baris Ozgul ,  Sneha Bhalchandra Date

IPC: H04L27/26 ,  G01R19/04 ,  G01R19/25

Abstract: Techniques related to a data processing engine for an integrated circuit (IC) are described. In an example, a method is provided for vectorized peak detection. The method includes dividing a set of data samples of a data signal, corresponding to a peak detection window (PDW), into a plurality of subsets of data samples each comprising a number of data samples. The method includes performing vector operations on each of the plurality of subsets of data samples. The method includes determining a running index of a sample with a maximum amplitude over the PDW based on the vector operations.

公开(公告)号：US20190303033A1

公开(公告)日：2019-10-03

申请号：US15944160

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Goran HK Bilski ,  Jan Langer ,  Baris Ozgul ,  Tim Tuan ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Christopher H. Dick

IPC: G06F3/06

Abstract: A device may include a plurality of data processing engines. Each of the data processing engines may include a core and a memory module. The plurality of data processing engines may be organized in a plurality of rows. Each core may be configured to communicate with other neighboring data processing engines of the plurality of data processing engines by shared access to the memory modules of the neighboring data processing engines.

公开(公告)号：US11853235B2

公开(公告)日：2023-12-26

申请号：US17826068

申请日：2022-05-26

Applicant: XILINX, INC.

Inventor： Juan J. Noguera Serra ,  Goran Hk Bilski ,  Baris Ozgul ,  Jan Langer

IPC: G06F13/16 ,  G06F12/084 ,  G06F9/54 ,  G11C8/16 ,  G06F15/167

CPC classification number: G06F13/1663 ,  G06F9/544 ,  G06F12/084 ,  G06F15/167 ,  G11C8/16

Abstract: Examples herein describe techniques for transferring data between data processing engines in an array using shared memory. In one embodiment, certain engines in the array have connections to the memory in neighboring engines. For example, each engine may have its own assigned memory module which can be accessed directly (e.g., without using a streaming or memory mapped interconnect). In addition, the surrounding engines (referred to herein as the neighboring engines) may also include direct connections to the memory module. Using these direct connections, the cores can load and/or store data in the neighboring memory modules.

公开(公告)号：US11443091B1

公开(公告)日：2022-09-13

申请号：US16945006

申请日：2020-07-31

Applicant: Xilinx, Inc.

Inventor： Peter McColgan ,  Baris Ozgul ,  David Clarke ,  Tim Tuan ,  Juan J. Noguera Serra ,  Goran H. K. Bilski ,  Jan Langer ,  Sneha Bhalchandra Date ,  Stephan Munz ,  Jose Marques

IPC: G06F30/343 ,  G06F9/30 ,  G06F30/398 ,  G06F30/33

Abstract: An integrated circuit includes a plurality of data processing engines (DPEs) DPEs. Each DPE may include a core configured to perform computations. A first DPE of the plurality of DPEs includes a first core coupled to an input cascade connection of the first core. The input cascade connection is directly coupled to a plurality of source cores of the plurality of DPEs. The input cascade connection includes a plurality of inputs, wherein each of the plurality of inputs is connected to a cascade output of a different one of the plurality of source cores. The input cascade connection is programmable to enable a selected one of the plurality of inputs.

公开(公告)号：US11372803B2

公开(公告)日：2022-06-28

申请号：US15944408

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran H. K. Bilski ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  David Clarke ,  Sneha Bhalchandra Date

IPC: G06F15/80 ,  G06F13/40 ,  G06F15/173 ,  G06F13/16

Abstract: An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes: a core; a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory; streaming interconnect coupled to the DMA circuitry and the core; and memory-mapped interconnect coupled to the core, the memory, and the support circuitry.

公开(公告)号：US11113223B1

公开(公告)日：2021-09-07

申请号：US15944490

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Peter McColgan ,  Goran H K Bilski ,  Juan J. Noguera Serra ,  Jan Langer ,  Baris Ozgul ,  David Clarke

IPC: G06F15/17 ,  G06F13/40 ,  H04L29/08 ,  H04L12/50 ,  H04L12/54 ,  H04L29/06 ,  G06F15/78 ,  G06F9/38

Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include streaming interconnects which transmit streaming data using two different modes: circuit switching and packet switching. Circuit switching establishes reserved point-to-point communication paths between endpoints in the interconnect which routes data in a deterministic manner. Packet switching, in contrast, transmits streaming data that includes headers for routing data within the interconnect in a non-deterministic manner. In one embodiment, the streaming interconnects can have one or more ports configured to perform circuit switching and one or more ports configured to perform packet switching.

公开(公告)号：US10747690B2

公开(公告)日：2020-08-18

申请号：US15944307

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran H K Bilski ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Philip B. James-Roxby ,  Christopher H. Dick

IPC: G06F15/78 ,  G06F13/16 ,  G06F13/40 ,  G06F15/173 ,  H04L12/933

Abstract: A device may include a plurality of data processing engines. Each data processing engine may include a core and a memory module. Each core may be configured to access the memory module in the same data processing engine and a memory module within at least one other data processing engine of the plurality of data processing engines.

公开(公告)号：US10579559B1

公开(公告)日：2020-03-03

申请号：US15944303

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran H K Bilski ,  Juan J. Noguera Serra ,  Jan Langer ,  Baris Ozgul

IPC: G06F13/24 ,  G06F11/22 ,  G06F13/28

Abstract: An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes a core, a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory, and a stall circuit coupled to the core configured to stall or resume the core in response to one or more inputs.