公开(公告)号：US11669464B1

公开(公告)日：2023-06-06

申请号：US16858417

申请日：2020-04-24

Applicant: XILINX, INC.

Inventor： Goran Hk Bilski ,  Baris Ozgul ,  David Clarke ,  Juan J. Noguera Serra ,  Jan Langer ,  Zachary Dickman ,  Sneha Bhalchandra Date ,  Tim Tuan

IPC: G06F12/1081 ,  G06F12/06 ,  G06F9/52 ,  G06F15/78 ,  G06F12/02

CPC classification number: G06F12/1081 ,  G06F9/524 ,  G06F12/0246 ,  G06F12/0607 ,  G06F15/7807

Abstract: Examples herein describe performing non-sequential DMA read and writes. Rather than storing data sequentially, a DMA engine can write data into memory using non-sequential memory addresses. A data processing engine (DPE) controller can submit a first job using first parameters that instruct the DMA engine to store data using a first non-sequential write pattern. The DPE controller can also submit a second job using second parameters that instruct the DMA engine to store data using a second, different non-sequential write pattern. In this manner, the DMA engine can switch to performing DMA writes using different non-sequential patterns. Similarly, the DMA engine can use non-sequential reads to retrieve data from memory. When performing a first DMA read, the DMA engine can retrieve data from memory using a first sequential pattern and then perform a second DMA read where data is retrieved from memory using a second non-sequential read pattern.

公开(公告)号：US11386020B1

公开(公告)日：2022-07-12

申请号：US16808054

申请日：2020-03-03

Applicant: XILINX, INC.

Inventor： Matthew H. Klein ,  Goran Hk Bilski ,  Juan Jose Noguera Serra ,  Ismed D. Hartanto ,  Sridhar Subramanian ,  Tim Tuan

IPC: G06F15/17 ,  G06F13/16 ,  G06F9/30 ,  H03K19/1776 ,  G06F7/501 ,  G06F15/173

Abstract: Some examples described herein relate to programmable devices that include a data processing engine (DPE) array that permits shifting of where an application is loaded onto DPEs of the DPE array. In an example, a programmable device includes a DPE array. The DPE array includes DPEs and address index offset logic. Each of the DPEs includes a processor core and a memory mapped switch. The processor core is programmable via one or more memory mapped packets routed through the respective memory mapped switch. The memory mapped switches in the DPE array are coupled together to form a memory mapped interconnect network. The address index offset logic is configurable to selectively modify which DPE in the DPE array is targeted by a respective memory mapped packet routed in the memory mapped interconnect network.

公开(公告)号：US11336287B1

公开(公告)日：2022-05-17

申请号：US17196574

申请日：2021-03-09

Applicant: Xilinx, Inc.

Inventor： Javier Cabezas Rodriguez ,  Juan J. Noguera Serra ,  David Clarke ,  Sneha Bhalchandra Date ,  Tim Tuan ,  Peter McColgan ,  Jan Langer ,  Baris Ozgul

IPC: H03K19/1776 ,  H03K19/17704 ,  H03K19/17768 ,  H03K19/17758 ,  H03K19/17796

Abstract: An integrated circuit can include a data processing engine (DPE) array having a plurality of tiles. The plurality of tiles can include a plurality of DPE tiles, wherein each DPE tile includes a stream switch, a core configured to perform operations, and a memory module. The plurality of tiles can include a plurality of memory tiles, wherein each memory tile includes a stream switch, a direct memory access (DMA) engine, and a random-access memory. The DMA engine of each memory tile may be configured to access the random-access memory within the same memory tile and the random-access memory of at least one other memory tile. Selected ones of the plurality of DPE tiles may be configured to access selected ones of the plurality of memory tiles via the stream switches.

公开(公告)号：US20220100691A1

公开(公告)日：2022-03-31

申请号：US17035368

申请日：2020-09-28

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Tim Tuan ,  Sridhar Subramanian

IPC: G06F13/40 ,  G06F13/16

Abstract: A multi-die integrated circuit (IC) can include an interposer and a first die coupled to the interposer. The first die can include a data processing engine (DPE) array, wherein the DPE array includes a plurality of DPEs and a DPE interface coupled to the plurality of DPEs. The DPE interface has a logical interface and a physical interface. The multi-die IC also can include a second die coupled to the interposer. The second die can include a die interface. The DPE interface and the die interface are configured to communicate through the interposer.

公开(公告)号：US20190303328A1

公开(公告)日：2019-10-03

申请号：US15944617

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran H.K. Balski ,  Juan J. Noguera Serra ,  David Clarke ,  Tim Tuan ,  Peter McColgan ,  Zachary Dickman ,  Baris Ozgul ,  Jan Langer

IPC: G06F13/40 ,  G06F13/16

Abstract: A device may include a plurality of data processing engines, a subsystem, and an SoC interface block coupled to the plurality of data processing engines and the subsystem. The SoC interface block may be configured to exchange data between the subsystem and the plurality of data processing engines.