公开(公告)号：US20130232351A1

公开(公告)日：2013-09-05

申请号：US13842128

申请日：2013-03-15

申请人： Stephen H. Gunther ,  Robert J. Greiner ,  Xia Dai ,  Hung-Piao MA

发明人： Stephen H. Gunther ,  Robert J. Greiner ,  Xia Dai ,  Hung-Piao MA

IPC分类号： G06F1/26 ,  G05F3/02

CPC分类号： G06F1/26 ,  F04D13/0666 ,  G05F3/02 ,  G06F1/20 ,  G06F2200/201 ,  G11B33/1413

摘要： The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.

公开(公告)号：US06631393B1

公开(公告)日：2003-10-07

申请号：US09002173

申请日：1997-12-31

申请人： Xia Dai

发明人： Xia Dai

IPC分类号： G06F750

CPC分类号： G06F7/508 ,  G06F2207/5063

摘要： One embodiment of the present invention, an eight bit binary adder with a typical latency independent of its width, is described. The adder comprises a four bit adder for calculating bits S3-S0 of the sum, plus four bitslice circuits, one for speculatively calculating each of bits S7-S4 of the sum. The calculation of the carry bit out of each bitslice is limited to the operands bits into that bitslice and the three preceding bitslices. Each bitslice also includes circuitry for detecting a potential error in the speculative sum such that the speculative sum can be corrected when there is a potential error.

摘要翻译： 描述了本发明的一个实施例，具有与其宽度无关的典型等待时间的八位二进制加法器。 加法器包括一个四位加法器，用于计算和的位S3-S0加上四个比特电路，一个用于推测计算和的每个比特S7-S4。 每个比特数据块中的进位位的计算被限制到该比特片段中的操作数比特和前面的三个比特片段。 每个位片还包括用于检测推测和中的潜在误差的电路，使得当存在潜在误差时可以校正推测和。

公开(公告)号：US06566913B2

公开(公告)日：2003-05-20

申请号：US09775770

申请日：2001-02-01

申请人： Xia Dai

发明人： Xia Dai

IPC分类号： G11C700

CPC分类号： H03K5/1534 ,  H03K3/356139

摘要： A method and apparatus for sensing logic signals is described. A single-ended sense amplifier may include a differential input with a data input transistor and a dummy input transistor. A controlled offset in the size of the data input transistor and the dummy input transistor may increase noise immunity and other performance attributes. A dummy complimentary path may include a partial set of complimentary transistors to a data set of transistors.

摘要翻译： 描述了用于感测逻辑信号的方法和装置。 单端读出放大器可以包括具有数据输入晶体管和虚拟输入晶体管的差分输入。 数据输入晶体管和虚拟输入晶体管的大小的受控偏移可能会增加抗噪声性能和其他性能属性。 虚拟补充路径可以包括与晶体管的数据集合的部分互补晶体管组。

公开(公告)号：US06311281B1

公开(公告)日：2001-10-30

申请号：US09261058

申请日：1999-03-02

申请人： Edwin J. Pole, II ,  John T. Orton ,  Cau L. Nguyen ,  Gurbir Singh ,  Xia Dai ,  Ravi Nagaraj

发明人： Edwin J. Pole, II ,  John T. Orton ,  Cau L. Nguyen ,  Gurbir Singh ,  Xia Dai ,  Ravi Nagaraj

IPC分类号： G06F104

CPC分类号： G06F1/08 ,  H03L7/06

摘要： A processor has an external pin that can be asserted to lock in new clock ratio information dynamically. A state machine of the processor defines a stop grant state that is utilized to halt the internal clocking signal of the processor. A storage location, such as a register, is utilized to load new clock frequency information into the clock generator circuit of the processor. De-asserting the external pin of the processor causes the processor to resume normal operations, but at the newly set clock frequency.

摘要翻译： 一个处理器有一个外部引脚，可以被断言，以动态锁定新的时钟比率信息。 处理器的状态机定义用于停止处理器的内部时钟信号的停止许可状态。 诸如寄存器的存储位置被用于将新的时钟频率信息加载到处理器的时钟发生器电路中。 取消断言处理器的外部引脚使处理器恢复正常操作，但处于新设定的时钟频率。

公开(公告)号：US06298105B1

公开(公告)日：2001-10-02

申请号：US09183031

申请日：1998-10-30

申请人： Xia Dai ,  George Geannopuolos ,  John Orton ,  Keng Wong ,  Greg F. Taylor

发明人： Xia Dai ,  George Geannopuolos ,  John Orton ,  Keng Wong ,  Greg F. Taylor

IPC分类号： H04L100

CPC分类号： G06F1/3287 ,  G06F1/10 ,  G06F1/3203 ,  H03L7/0814 ,  H03L7/087 ,  Y02D10/171

摘要： An apparatus for a low skew, low standby power clock network for a synchronous digital system. The power clock network comprises a reference network, maintaining a reference clock signal, and four clock spines, each with its own respective clock signal. To reduce clock skew within the power clock network (i.e., to keep the clock signals of the clock spines synchronous with the reference clock signal), the present invention employs the use of active and passive delay elements to compensate for such skew. A phase relation extraction logic compares the phase of the clock signals from each respective clock spine to the reference clock signal of the reference network. If it is determined that the clock signals of the spines lag the reference clock signal, the phase relation extraction logic will use an active control driver to “speed-up” the clock signals of the clock spines. And, if the clock signals of the clock spines lead the reference clock signal, the phase relation extraction logic will use capacitive loadings to “slow down” such clock signals. Advantageously, the likelihood of the microprocessor achieving its maximum operating potential is greatly enhanced by the synchronization of such signals.

摘要翻译： 一种用于同步数字系统的低偏移，低待机功率时钟网络的装置。 功率时钟网络包括参考网络，维护参考时钟信号和四个时钟棘轮，每个具有其各自的时钟信号。 为了减少功率时钟网络内的时钟偏移（即，使时钟的时钟信号与参考时钟信号保持同步），本发明采用有源和无源延迟元件来补偿这种偏移。 相位关系提取逻辑将来自每个相应时钟脊的时钟信号的相位与参考网络的参考时钟信号进行比较。 如果确定脊柱的时钟信号滞后于参考时钟信号，则相位关系提取逻辑将使用主动控制驱动器来“加速”时钟棘轮的时钟信号。 而且，如果时钟的时钟信号引导参考时钟信号，则相位关系提取逻辑将使用电容负载来“减慢”这样的时钟信号。 有利地，通过这种信号的同步，微处理器实现其最大工作电位的可能性大大提高。

公开(公告)号：US06272642B1

公开(公告)日：2001-08-07

申请号：US09204896

申请日：1998-12-03

申请人： Edwin J. Pole, II ,  Scott R. Rushford ,  Eric S. Swartzendruber ,  Xia Dai

发明人： Edwin J. Pole, II ,  Scott R. Rushford ,  Eric S. Swartzendruber ,  Xia Dai

IPC分类号： G06F126

摘要： A system includes a component, a detector adapted to detect generation of a power management event, and a controller adapted to transition the component from a first performance mode to a lower activity state in response to the power management event. The controller is adapted to change a setting of the component to a second, different performance mode while the component is in the lower activity state. The power management event may be generated in response to a change in the system's power source, an over-temperature condition, or a user command.

公开(公告)号：US06211740B1

公开(公告)日：2001-04-03

申请号：US09408134

申请日：1999-09-29

申请人： Xia Dai ,  Keng Wong

发明人： Xia Dai ,  Keng Wong

IPC分类号： H03L707

CPC分类号： G06F1/08 ,  H03L7/07 ,  H03L7/081 ,  H03L7/0891 ,  H03L7/23

摘要： Switching a clocked device from an initial frequency to a target frequency includes locking a first phase locked loop (PLL) to the target frequency while a second PLL is driving a clock distribution network at the initial frequency. The first PLL is then substituted for the second PLL on the clock distribution network.

摘要翻译： 将时钟设备从初始频率切换到目标频率包括将第一锁相环（PLL）锁定到目标频率，而第二PLL以初始频率驱动时钟分配网络。 然后，第一个PLL代替时钟分配网络上的第二个PLL。

公开(公告)号：US6075832A

公开(公告)日：2000-06-13

申请号：US946671

申请日：1997-10-07

申请人： George Geannopoulos ,  Keng L. Wong ,  Greg F. Taylor ,  Xia Dai

发明人： George Geannopoulos ,  Keng L. Wong ,  Greg F. Taylor ,  Xia Dai

IPC分类号： G06F1/10 ,  H03D3/24 ,  H03D13/00 ,  H03L7/00 ,  H03L7/081 ,  H03L7/087

CPC分类号： H03L7/087 ,  G06F1/10 ,  H03L7/0814

摘要： An apparatus for deskewing clock signals in a synchronous digital system. The apparatus contains a phase detection circuit that receives a plurality of clock signals and generates an output based on a phase relationship between those clock signals. A controller then receives the output of the phase detector and determines which one of the plurality of clock signals requires adjustment based on the output of the phase detector and a bit from a delay shift register. The controller transmits a delay signal to one of a plurality of delay circuits which modifies the delay of the clock signal that the controller determined to require adjustment.

摘要翻译： 一种在同步数字系统中对时钟信号进行偏移校正的装置。 该装置包含相位检测电路，其接收多个时钟信号，并根据这些时钟信号之间的相位关系产生输出。 然后，控制器接收相位检测器的输出，并且基于相位检测器的输出和来自延迟移位寄存器的位确定多个时钟信号中的哪一个需要调整。 控制器将延迟信号发送到多个延迟电路中的一个，其修改控制器确定需要调整的时钟信号的延迟。