公开(公告)号：US20130232351A1

公开(公告)日：2013-09-05

申请号：US13842128

申请日：2013-03-15

申请人： Stephen H. Gunther ,  Robert J. Greiner ,  Xia Dai ,  Hung-Piao MA

发明人： Stephen H. Gunther ,  Robert J. Greiner ,  Xia Dai ,  Hung-Piao MA

IPC分类号： G06F1/26 ,  G05F3/02

CPC分类号： G06F1/26 ,  F04D13/0666 ,  G05F3/02 ,  G06F1/20 ,  G06F2200/201 ,  G11B33/1413

摘要： The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.

公开(公告)号：US06208169B1

公开(公告)日：2001-03-27

申请号：US09340975

申请日：1999-06-28

申请人： Keng L. Wong ,  Gregory F. Taylor ,  Ravishankar Kuppuswamy ,  Douglas R. Parker ,  Hung-Piao Ma ,  Kent R. Callahan ,  Xia Dai

发明人： Keng L. Wong ,  Gregory F. Taylor ,  Ravishankar Kuppuswamy ,  Douglas R. Parker ,  Hung-Piao Ma ,  Kent R. Callahan ,  Xia Dai

IPC分类号： H03K19096

CPC分类号： H03L7/091 ,  H03L7/0814

摘要： An apparatus and method for detecting and measuring internal clock jitter is disclosed. In one embodiment, a reference clock generator generates a reference clock signal based on an instantaneous clock signal. The reference clock signal includes the instantaneous clock signal delayed for an average duration. A phase comparing element receives both the instantaneous clock signal and the reference clock signal such that the phase comparing element measures a phase difference between the instantaneous clock signal and the reference clock signal. The magnitude and direction of the phase difference is indicated by one of a number of distinct phase difference bins in the phase comparing element.

摘要翻译： 公开了一种用于检测和测量内部时钟抖动的装置和方法。 在一个实施例中，参考时钟发生器基于瞬时时钟信号产生参考时钟信号。 参考时钟信号包括延迟平均持续时间的瞬时时钟信号。 相位比较元件接收瞬时时钟信号和参考时钟信号，使得相位比较元件测量瞬时时钟信号和参考时钟信号之间的相位差。 相位差的幅度和方向由相位比较元件中的多个不同的相位差区之一表示。

公开(公告)号：US06988211B2

公开(公告)日：2006-01-17

申请号：US09751528

申请日：2000-12-29

申请人： Leslie E. Cline ,  Xia Dai ,  Varghese George ,  Robert L. Farrell

发明人： Leslie E. Cline ,  Xia Dai ,  Varghese George ,  Robert L. Farrell

IPC分类号： G06F1/26

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A selectable control over multiple clock frequency/voltage level combinations that can be activated in a processor. A table can be placed in hardware that defines multiple combinations of CPU clock frequency and CPU operating voltage. By placing the table in hardware, it can be assured that all the various combinations will work for the particular processor device. Software can then be used to select a combination from this table, to control the actual frequency/voltage combination that is being implemented at a given time. This allows dynamic control over the power/performance tradeoff, so that the system can see maximum power savings consistent with acceptable performance, as operating and environmental considerations continue to change the most desirable selections.

摘要翻译： 可以在处理器中激活的多个时钟频率/电压电平组合的可选择控制。 一个表可以放置在硬件中，定义了CPU时钟频率和CPU工作电压的多种组合。 通过将表放置在硬件中，可以确保所有各种组合都适用于特定的处理器设备。 然后可以使用软件从该表中选择组合，以控制在给定时间正在实施的实际频率/电压组合。 这允许对功率/性能的权衡进行动态控制，使得系统可以看到与可接受的性能一致的最大功率节省，因为操作和环境考虑继续改变最理想的选择。

公开(公告)号：US06738675B2

公开(公告)日：2004-05-18

申请号：US09751727

申请日：2000-12-30

申请人： Xia Dai

发明人： Xia Dai

IPC分类号： G05B1101

CPC分类号： G06F1/3203 ,  G06F12/0831 ,  G06F2212/1028 ,  Y02D10/13

摘要： A method and apparatus for reducing a microprocessor's power dissipation. In one embodiment a microprocessor includes a clock circuit, a core coupled to said clock circuit, and an on-die logic circuit coupled to said clock circuit to operate independent of a connection for power to said core, the on-die logic circuit includes a snoop request monitor coupled to a bus, and a snooping memory circuit.

摘要翻译： 一种降低微处理器功耗的方法和装置。 在一个实施例中，微处理器包括时钟电路，耦合到所述时钟电路的芯和耦合到所述时钟电路的片上逻辑电路，以独立于用于所述核的功率的连接来工作，片上逻辑电路包括 连接到总线的监听请求监视器和窥探存储器电路。

公开(公告)号：US09501773B2

公开(公告)日：2016-11-22

申请号：US13018375

申请日：2011-01-31

申请人： Xia Dai

发明人： Xia Dai

IPC分类号： G06Q40/00 ,  G06Q20/40

CPC分类号： G06Q20/4016 ,  G06F21/64 ,  G06Q20/204 ,  G06Q20/209 ,  G06Q20/3224 ,  G06Q20/40 ,  H04W4/021 ,  H04W4/80 ,  H04W12/06 ,  H04W12/12

摘要： The present invention relates to a secured transaction system. In one embodiment, a mobile transaction processing agent system includes a communication module configured to receive a secured transaction description from a mobile client device or an encrypted transaction description from a point-of-sale (POS) device, wherein the secured transaction description is in the form of a bar code generated by the mobile client device, an authentication module configured to decode the secured transaction description and verify the secured transaction description is valid based on the mobile client device or the point-of-sale device, and a transaction processing module configured to process the transaction in accordance with the secured transaction description.

摘要翻译： 本发明涉及一种安全的交易系统。 在一个实施例中，移动交易处理代理系统包括被配置为从移动客户端设备接收安全交易描述的通信模块或来自销售点（POS）设备的加密交易描述，其中所述担保交易描述处于 由移动客户端设备生成的条形码的形式，被配置为解码安全交易描述并验证安全交易描述的认证模块基于移​​动客户端设备或销售点设备以及交易处理 模块被配置为根据安全的交易描述处理交易。

公开(公告)号：US06704880B2

公开(公告)日：2004-03-09

申请号：US09978644

申请日：2001-10-18

申请人： Xia Dai ,  Borys S. Senyk

发明人： Xia Dai ,  Borys S. Senyk

IPC分类号： G06F132

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/3296 ,  G06F12/0891 ,  Y02D10/128 ,  Y02D10/172

摘要： Leakage power consumption may be reduced in computers and other devices by providing a state where clocks are off and a low supply voltage is provided to the processor. This voltage may be sufficiently low to prevent adverse consequences while dramatically reducing leakage current. In addition, caches may be flushed to reduce the soft error rate.

摘要翻译： 通过提供时钟关闭状态和向处理器提供低电源电压的状态，计算机和其他设备中的泄漏功耗可能会降低。 该电压可能足够低以防止不利后果，同时显着减少漏电流。 此外，可以刷新缓存以减少软错误率。

公开(公告)号：US07225347B2

公开(公告)日：2007-05-29

申请号：US11300716

申请日：2005-12-13

申请人： Xia Dai ,  John W. Horigan ,  Millind Mittal ,  Leslie E. Cline

发明人： Xia Dai ,  John W. Horigan ,  Millind Mittal ,  Leslie E. Cline

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F12/0891

摘要： In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicated the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.

摘要翻译： 根据本发明的实施例，启动触发事件以将处理器置于低功率状态。 根据电源状态信号，处理器可能进入或不进入低功率状态时刷新高速缓存。 功率状态信号可以指示与将低处理器置于低功率状态相关联的功率降低的相对优先级，而无需首先刷新高速缓存，而与高功率状态中的电压降低相关联的高速缓存中的软错误率的增加。

公开(公告)号：US20060095806A1

公开(公告)日：2006-05-04

申请号：US11300716

申请日：2005-12-13

申请人： Xia Dai ,  John Horigan ,  Millind Mittal ,  Leslie Cline

发明人： Xia Dai ,  John Horigan ,  Millind Mittal ,  Leslie Cline

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F12/0891

摘要： In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicated the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.

摘要翻译： 根据本发明的实施例，启动触发事件以将处理器置于低功率状态。 根据电源状态信号，处理器可能进入或不进入低功率状态时刷新高速缓存。 功率状态信号可以指示与将低处理器置于低功率状态相关联的功率降低的相对优先级，而无需首先刷新高速缓存，而与高功率状态中的电压降低相关联的高速缓存中的软错误率的增加。

公开(公告)号：US06792551B2

公开(公告)日：2004-09-14

申请号：US09995171

申请日：2001-11-26

申请人： Xia Dai

发明人： Xia Dai

IPC分类号： G06F132

CPC分类号： G06F1/3203

摘要： In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The voltage from a first voltage regulator supplied to a core of the processor may be lowered to a level at which the processor core becomes non-operational and the processor state is lost. The processor may include a memory region in which the processor state may be stored upon entering the low power state. This memory region may be powered by a second voltage regulator so that its contents are not lost while in the low power state. For one embodiment of the present invention, the processor may additionally include a snoop controller powered by the second voltage regulator. This snoop controller may snoop a cache, which may also be powered by the second voltage regulator, while the processor is in the low power state. The snoop controller may additionally monitor interrupts.

摘要翻译： 根据本发明的实施例，启动触发事件以将处理器置于低功率状态。 提供给处理器的核心的第一电压调节器的电压可以降低到处理器核心变得不可操作并且处理器状态丢失的水平。 处理器可以包括其中在进入低功率状态时可以存储处理器状态的存储器区域。 该存储器区域可以由第二电压调节器供电，使得其在低功率状态下不会丢失。 对于本发明的一个实施例，处理器可另外包括由第二电压调节器供电的监听控制器。 该侦听控制器可以在处理器处于低功率状态时窥探高速缓存，高速缓存也可由第二电压调节器供电。 监听控制器可以另外监视中断。

公开(公告)号：US06573772B1

公开(公告)日：2003-06-03

申请号：US09608485

申请日：2000-06-30

申请人： Xia Dai ,  Thomas D. Fletcher

发明人： Xia Dai ,  Thomas D. Fletcher

IPC分类号： G11C700

CPC分类号： H03K5/1534 ,  H03K3/356139

摘要： A method and apparatus for generating multiple locked self-timed pulsed clock signals is disclosed. Race margins are reduced over separate clock generating circuits by sharing the necessary delay circuit elements between the multiple clock generating circuits. An edge is gated with a delayed edge to form the first clock pulse. A subsequent second clock pulse is generated by gating a partially-delayed edge with the first clock pulse, which minimizes race margins and pulse evaporation.

摘要翻译： 公开了一种用于产生多个锁定自定时脉冲时钟信号的方法和装置。 通过在多个时钟发生电路之间共享必要的延迟电路元件，在单独的时钟发生电路上减少了占空比。 边沿通过延迟边缘选通以形成第一个时钟脉冲。 通过使用第一时钟脉冲选通部分延迟的边缘来产生随后的第二时钟脉冲，其使竞赛边缘和脉冲蒸发最小化。