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28 条记录 (耗时 0.031 秒)

    BUILT-IN SELF-TEST FOR INTERPOSER
    22.
    发明申请
    BUILT-IN SELF-TEST FOR INTERPOSER 有权
    内置自检测试

    公开(公告)号：US20130047049A1

    公开(公告)日：2013-02-21

    申请号：US13209477

    申请日：2011-08-15

    申请人： Ji-Jan CHEN ,  Nan-Hsin Tseng ,  Chin-Chou Liu

    发明人： Ji-Jan CHEN ,  Nan-Hsin Tseng ,  Chin-Chou Liu

    IPC分类号： G01R31/3187 ,  G06F11/27

    CPC分类号： G01R31/318536

    摘要： A device includes a first die coupled to an interconnect structure of an interposer. The first die includes a first BIST circuit configured to generate and output test signals to the interconnection structure of the interposer. A second die is coupled to the interconnect structure of the interposer and includes a second BIST circuit configured to receive signals from the interconnection structure of the interposer in response to the first BIST circuit transmitting the test signals. The second BIST circuit is configured to compare the signals received from the interconnection structure of the interposer to reference signals generated by the second BIST circuit.

    摘要翻译： 器件包括耦合到插入器的互连结构的第一管芯。 第一裸片包括第一BIST电路，其被配置为产生并输出测试信号到中介层的互连结构。 第二管芯耦合到插入器的互连结构，并且包括第二BIST电路，其被配置为响应于第一BIST电路发送测试信号而从插入器的互连结构接收信号。 第二BIST电路被配置为将从插入器的互连结构接收的信号与由第二BIST电路产生的参考信号进行比较。

    Ultra high resolution timing measurement
    23.
    发明授权
    Ultra high resolution timing measurement 有权
    超高分辨率时序测量

    公开(公告)号：US08305847B2

    公开(公告)日：2012-11-06

    申请号：US13110735

    申请日：2011-05-18

    申请人： Nan-Hsin Tseng ,  Chin-Chou Liu ,  Saurabh Gupta

    发明人： Nan-Hsin Tseng ,  Chin-Chou Liu ,  Saurabh Gupta

    IPC分类号： G04F8/00 ,  G01R13/02

    CPC分类号： G04F10/005

    摘要： A method for high-resolution timing measurement includes a first oscillator generating a first clock with a first frequency. A second oscillator generates a second clock with a second frequency. A delay pulse generator generates a delayed pulse from the second clock. An oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the first frequency. A sampling module samples the delayed pulse at the first frequency. A counter generates a digital counter value by counting a number of samples made by the sampling module.

    摘要翻译： 用于高分辨率定时测量的方法包括产生具有第一频率的第一时钟的第一振荡器。 第二振荡器产生具有第二频率的第二时钟。 延迟脉冲发生器从第二时钟产生延迟的脉冲。 振荡器调谐器控制第二频率尽可能接近于第一频率，而不与第一频率相同。 采样模块以第一个频率采样延迟脉冲。 计数器通过对由采样模块进行的采样数进行计数来产生数字计数器值。

    Switched capacitor comparator circuit
    26.
    发明授权
    Switched capacitor comparator circuit 有权
    开关电容比较电路

    公开(公告)号：US09557354B2

    公开(公告)日：2017-01-31

    申请号：US13362576

    申请日：2012-01-31

    申请人： Chih-Chia Chen ,  Kuan-Yu Lin ,  Chin-Chou Liu

    发明人： Chih-Chia Chen ,  Kuan-Yu Lin ,  Chin-Chou Liu

    IPC分类号： G01R19/165 ,  H03K5/24 ,  G01R31/3185 ,  G01R31/28

    CPC分类号： G01R19/16552 ,  G01R31/2856 ,  G01R31/318513 ,  H03K5/24

    摘要： A circuit including a first switch receiving an input reference voltage, a second switch receiving an input testing voltage, the first switch and the second switch are electrically connected in parallel. The circuit further includes a first capacitor electrically connected in series with the first switch and the second switch. The circuit further includes a feedback stage comprising a feedback inverter electrically connected in parallel with a feedback switch, where the feedback stage is electrically connected in series with the first capacitor. The circuit further includes a first inverter electrically connected in series to the feedback stage, and a third switch electrically connected in series with the first inverter. The circuit further includes a second inverter electrically connected in parallel to a third inverter, the second inverter and the third inverter are electrically connected in series to the third switch, and the third inverter outputs a first output signal.

    摘要翻译： 包括接收输入参考电压的第一开关，接收输入测试电压的第二开关，第一开关和第二开关的电路并联电连接。 电路还包括与第一开关和第二开关串联电连接的第一电容器。 电路还包括反馈级，其包括与反馈开关并联电连接的反馈反相器，其中反馈级与第一电容器串联电连接。 电路还包括与反馈级串联电连接的第一反相器和与第一反相器串联电连接的第三开关。 电路还包括与第三反相器并联电连接的第二反相器，第二反相器和第三反相器与第三开关串联电连接，并且第三反相器输出第一输出信号。

    Built-in self-test for interposer
    27.
    发明授权
    Built-in self-test for interposer 有权
    内置自检功能

    公开(公告)号：US08832511B2

    公开(公告)日：2014-09-09

    申请号：US13209477

    申请日：2011-08-15

    申请人： Ji-Jan Chen ,  Nan-Hsin Tseng ,  Chin-Chou Liu

    发明人： Ji-Jan Chen ,  Nan-Hsin Tseng ,  Chin-Chou Liu

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318536

    摘要： A device includes a first die coupled to an interconnect structure of an interposer. The first die includes a first BIST circuit configured to generate and output test signals to the interconnection structure of the interposer. A second die is coupled to the interconnect structure of the interposer and includes a second BIST circuit configured to receive signals from the interconnection structure of the interposer in response to the first BIST circuit transmitting the test signals. The second BIST circuit is configured to compare the signals received from the interconnection structure of the interposer to reference signals generated by the second BIST circuit.

    摘要翻译： 器件包括耦合到插入器的互连结构的第一管芯。 第一裸片包括第一BIST电路，其被配置为产生并输出测试信号到中介层的互连结构。 第二管芯耦合到插入器的互连结构，并且包括第二BIST电路，其被配置为响应于第一BIST电路发送测试信号而从插入器的互连结构接收信号。 第二BIST电路被配置为将从插入器的互连结构接收的信号与由第二BIST电路产生的参考信号进行比较。