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    NAND FLASH MEMORY DEVICE HAVING DUMMY MEMORY CELLS AND METHODS OF OPERATING SAME
    22.
    发明申请
    NAND FLASH MEMORY DEVICE HAVING DUMMY MEMORY CELLS AND METHODS OF OPERATING SAME 有权
    具有存储单元的NAND闪速存储器件及其操作方法

    公开(公告)号：US20090097326A1

    公开(公告)日：2009-04-16

    申请号：US12340250

    申请日：2008-12-19

    申请人： Ki-Tae Park ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yoo-Cheol Shin

    发明人： Ki-Tae Park ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yoo-Cheol Shin

    IPC分类号： G11C16/06

    CPC分类号： G11C16/0483 ,  G11C16/107 ,  G11C16/12 ,  G11C16/3445

    摘要： A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.

    摘要翻译： NAND闪速存储器件包括控制电路，其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压，第二字线电压大于第一字线电压 到多个存储单元中的一个选择的一个，以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。 在其他实施例中，控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。 在其他实施例中，控制电路被配置为在擦除与其串联连接的多个存储器单元时，放弃擦除伪存储器单元。

    Methods of forming nonvolatile memory devices
    23.
    发明授权
    Methods of forming nonvolatile memory devices 有权
    形成非易失性存储器件的方法

    公开(公告)号：US07399672B2

    公开(公告)日：2008-07-15

    申请号：US11375983

    申请日：2006-03-15

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    IPC分类号： H01L21/336

    CPC分类号： H01L27/105 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568

    摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.

    摘要翻译： 形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。 在电阻器区域中的器件隔离层上形成第一导电层。 半导体衬底暴露在电池阵列区域中。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分上形成电池绝缘层。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。 蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

    Nonvolatile memory devices and methods of forming the same
    25.
    发明申请
    Nonvolatile memory devices and methods of forming the same 有权
    非易失存储器件及其形成方法

    公开(公告)号：US20060208338A1

    公开(公告)日：2006-09-21

    申请号：US11375983

    申请日：2006-03-15

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    IPC分类号： H01L29/00

    CPC分类号： H01L27/105 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568

    摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.

    摘要翻译： 形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。 在电阻器区域中的器件隔离层上形成第一导电层。 半导体衬底暴露在电池阵列区域中。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分上形成电池绝缘层。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。 蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

    Non-volatile memory device having charge trap layer and method of fabricating the same
    26.
    发明申请
    Non-volatile memory device having charge trap layer and method of fabricating the same 审中-公开
    具有电荷陷阱层的非易失性存储器件及其制造方法

    公开(公告)号：US20060208302A1

    公开(公告)日：2006-09-21

    申请号：US11354535

    申请日：2006-02-15

    申请人： Yoo-Cheol Shin ,  Jung-Dal Choi ,  Ki-Tae Park ,  Jong-Sun Sel

    发明人： Yoo-Cheol Shin ,  Jung-Dal Choi ,  Ki-Tae Park ,  Jong-Sun Sel

    IPC分类号： H01L29/76

    CPC分类号： H01L29/66833 ,  H01L29/792

    摘要： A non-volatile memory device having a charge trap layer and a method of fabricating the same are provided. The non-volatile memory device includes a semiconductor substrate having an active region and a field region in contact with the active region. A trench isolation layer is formed within the semiconductor substrate field region to define the active region and has a protrusion higher than a top surface of the semiconductor substrate active region. A memory storage pattern is formed which crosses and extends from the semiconductor substrate active region to cover sidewalls of the protrusion of the trench isolation layer. A gate electrode is formed on the memory storage pattern and extends upward from the trench isolation layer.

    摘要翻译： 提供了具有电荷陷阱层的非易失性存储器件及其制造方法。 非易失性存储器件包括具有有源区和与有源区接触的场区的半导体衬底。 沟槽隔离层形成在半导体衬底场区内，以限定有源区，并具有高于半导体衬底有源区的顶表面的突起。 形成存储器存储图案，其跨越并从半导体衬底有源区域延伸以覆盖沟槽隔离层的突起的侧壁。 栅电极形成在存储器存储图案上并从沟槽隔离层向上延伸。

    Methods of fabricating contact holes for integrated circuit substrates by etching to define a sidewall and concurrently forming a polymer on the sidewall
    27.
    发明授权
    Methods of fabricating contact holes for integrated circuit substrates by etching to define a sidewall and concurrently forming a polymer on the sidewall 有权
    通过蚀刻来制造用于集成电路基板的接触孔以限定侧壁并同时在侧壁上形成聚合物的方法

    公开(公告)号：US6028001A

    公开(公告)日：2000-02-22

    申请号：US273890

    申请日：1999-03-22

    申请人： Yoo-Cheol Shin

    发明人： Yoo-Cheol Shin

    IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/76816

    摘要： A contact hole for an integrated circuit substrate is fabricated by forming first and second layers on an integrated circuit substrate and a photoresist pattern on the second layer including a first opening therein. The second layer is etched through the first opening to define a sidewall therein while concurrently forming a polymer on the sidewall, so as to form a second opening in the second layer that is smaller than the first opening. The etching step preferably comprises the step of etching the second layer using a fluorocarbon to define a sidewall therein while concurrently forming a fluorocarbon polymer on the sidewall. The first layer is then etched through the second opening to form the contact hole to the integrated circuit substrate. A conductive layer may be formed in the contact hole to form a conductive contact that electrically contacts the integrated circuit substrate. Accordingly, by concurrently etching the second layer and forming a polymer on the etched sidewall thereof, smaller openings may be formed in the second layer than are formed in the photoresist pattern thereon.

    摘要翻译： 通过在集成电路基板上形成第一层和第二层上的光致抗蚀剂图案，其中包括第一开口，制造用于集成电路基板的接触孔。 通过第一开口蚀刻第二层以在其中限定侧壁，同时在侧壁上形成聚合物，以在第二层中形成小于第一开口的第二开口。 蚀刻步骤优选包括使用氟碳化合物蚀刻第二层以在其中限定侧壁的步骤，同时在侧壁上形成氟碳聚合物。 然后通过第二开口蚀刻第一层以形成到集成电路基板的接触孔。 可以在接触孔中形成导电层以形成与集成电路基板电接触的导电接触。 因此，通过同时蚀刻第二层并在其蚀刻的侧壁上形成聚合物，可以在第二层中形成比在其上的光致抗蚀剂图案中形成的更小的开口。

    Semiconductor device having air gap and method of fabricating the same
    28.
    发明授权
    Semiconductor device having air gap and method of fabricating the same 有权
    具有气隙的半导体装置及其制造方法

    公开(公告)号：US08575680B2

    公开(公告)日：2013-11-05

    申请号：US13564117

    申请日：2012-08-01

    申请人： Yoo-Cheol Shin ,  Joon-Hee Lee

    发明人： Yoo-Cheol Shin ,  Joon-Hee Lee

    IPC分类号： H01L29/788

    CPC分类号： H01L21/764 ,  H01L27/11521

    摘要： A semiconductor device includes tunneling insulating layers on active regions of a substrate, floating gate electrodes on the tunneling insulating layers, an isolation trench within the substrate and the isolation trench defines the active region, spaces the tunneling insulating layers, and isolates the floating gate electrodes. A bottom of the isolation trench is directly in contact with the substrate. The semiconductor device further includes a lower insulating layer on the floating gate electrodes, and a middle insulating layer, an upper insulating layer, and a control gate electrode stacked on the lower insulating layer. The lower insulating layer is configured to hermetically seal a top portion of the isolation trench to define and directly abut an air gap within the isolation trench.

    摘要翻译： 半导体器件包括在衬底的有源区上的隧道绝缘层，隧道绝缘层上的浮动栅电极，衬底内的隔离沟槽，隔离沟槽限定有源区，使隧道绝缘层隔开，并隔离浮置栅电极 。 隔离沟槽的底部直接与衬底接触。 半导体器件还包括浮置栅电极上的下绝缘层，以及堆叠在下绝缘层上的中间绝缘层，上绝缘层和控制栅电极。 下绝缘层被配置为气密地密封隔离沟槽的顶部以限定和直接邻接隔离沟槽内的气隙。

    Semiconductor Device With Resistor Pattern And Method Of Fabricating The Same
    30.
    发明申请
    Semiconductor Device With Resistor Pattern And Method Of Fabricating The Same 审中-公开
    具有电阻图案的半导体器件及其制造方法

    公开(公告)号：US20110309433A1

    公开(公告)日：2011-12-22

    申请号：US13223689

    申请日：2011-09-01

    申请人： Yoo-Cheol Shin

    发明人： Yoo-Cheol Shin

    IPC分类号： H01L29/792

    CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/10897 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11568 ,  Y10S257/904

    摘要： Disclosed is a semiconductor device with a resistor pattern and methods of fabricating the same. Embodiments of the present invention provide a method of fabricating a resistor pattern having high sheet resistance by using a polycide layer for a gate electrode in a semiconductor device with the resistor pattern. Embodiments of the invention also provide a semiconductor device with a resistor pattern that is formed narrower than the minimum line width that can be defined in a photolithographic process so that sheet resistance thereof increases, and a method of fabricating the same.

    摘要翻译： 公开了具有电阻图案的半导体器件及其制造方法。 本发明的实施例提供一种通过在具有电阻图案的半导体器件中使用用于栅电极的多晶硅化层来制造具有高薄层电阻的电阻器图案的方法。 本发明的实施例还提供了一种半导体器件，其具有比可以在光刻工艺中限定的最小线宽窄的电阻器图案，使得其电阻值增加，并且其制造方法。