公开(公告)号：US07452776B1

公开(公告)日：2008-11-18

申请号：US11739482

申请日：2007-04-24

申请人： Yue-Song He ,  Len Mei

发明人： Yue-Song He ,  Len Mei

IPC分类号： H01L21/8247

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7854 ,  H01L29/7881

摘要： A floating gate memory cell's channel region (104) is at least partially located in a fin-like protrusion (110P) of a semiconductor substrate. The floating gate's top surface may come down along at least two sides of the protrusion to a level below the top (110P-T) of the protrusion. The control gate's bottom surface may also comes down to a level below the top of the protrusion. The floating gate's bottom surface may comes down to a level below the top of the protrusion by at least 50% of the protrusion's height. The dielectric (120) separating the floating gate from the protrusion can be at least as thick at the top of the protrusion as at a level (L2) which is below the top of the protrusion by at least 50% of the protrusion's height. A very narrow fin or other narrow feature in memory and non-memory integrated circuits can be formed by providing a first layer (320) and then forming spacers (330) from a second layer without photolithography on sidewalls of features made from the first layer. The narrow fin or other feature are then formed without further photolithography in areas between the adjacent spacers. More particularly, a third layer (340) is formed in these areas, and the first layer and the spacers are removed selectively to the third layer. The third layer is used as a mask to form the narrow features.

摘要翻译： 浮栅存储单元的沟道区（104）至少部分地位于半导体衬底的鳍状突起（110P）中。 浮栅的顶面可以沿着突起的至少两侧下降到突起的顶部（110P-T）下方的水平面。 控制门的底面也可能下降至低于突起顶部的水平。 浮动门的底面可能下降到突起顶部以下至少50％的高度。 将浮动栅极与突起分离的电介质（120）可以在突起的顶部处至少与在突起的顶部下方高达突起高度的50％的水平面（L 2）一样厚。 存储器和非存储器集成电路中的非常狭窄的鳍或其他窄特征可以通过提供第一层（320）然后从第二层形成间隔物（330）而形成，而不需要在由第一层制成的特征的侧壁上进行光刻。 然后在相邻间隔物之间​​的区域中形成窄鳍片或其它特征，而无需进一步的光刻。 更具体地，在这些区域中形成第三层（340），并且第一层和间隔物被选择性地去除到第三层。 第三层用作掩模以形成窄特征。

公开(公告)号：US20080266949A1

公开(公告)日：2008-10-30

申请号：US11739482

申请日：2007-04-24

申请人： Yue-Song He ,  Len Mei

发明人： Yue-Song He ,  Len Mei

IPC分类号： G11C11/34 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7854 ,  H01L29/7881

摘要： A floating gate memory cell's channel region (104) is at least partially located in a fin-like protrusion (110P) of a semiconductor substrate. The floating gate's top surface may come down along at least two sides of the protrusion to a level below the top (110P-T) of the protrusion. The control gate's bottom surface may also comes down to a level below the top of the protrusion. The floating gate's bottom surface may comes down to a level below the top of the protrusion by at least 50% of the protrusion's height. The dielectric (120) separating the floating gate from the protrusion can be at least as thick at the top of the protrusion as at a level (L2) which is below the top of the protrusion by at least 50% of the protrusion's height. A very narrow fin or other narrow feature in memory and non-memory integrated circuits can be formed by providing a first layer (320) and then forming spacers (330) from a second layer without photolithography on sidewalls of features made from the first layer. The narrow fin or other feature are then formed without further photolithography in areas between the adjacent spacers. More particularly, a third layer (340) is formed in these areas, and the first layer and the spacers are removed selectively to the third layer. The third layer is used as a mask to form the narrow features.

摘要翻译： 浮栅存储单元的沟道区（104）至少部分地位于半导体衬底的鳍状突起（110P）中。 浮栅的顶面可以沿着突起的至少两侧下降到突起的顶部（110P-T）下方的水平面。 控制门的底面也可能下降至低于突起顶部的水平。 浮动门的底面可能下降到突起顶部以下至少50％的高度。 将浮动栅极与突起分离的电介质（120）可以在突起的顶部处至少与在突起的顶部下方高达突起高度的50％的水平面（L 2）一样厚。 存储器和非存储器集成电路中的非常狭窄的鳍或其他窄特征可以通过提供第一层（320）然后从第二层形成间隔物（330）而形成，而不需要在由第一层制成的特征的侧壁上进行光刻。 然后在相邻间隔物之间​​的区域中形成窄鳍片或其它特征，而无需进一步的光刻。 更具体地，在这些区域中形成第三层（340），并且第一层和间隔物被选择性地去除到第三层。 第三层用作掩模以形成窄特征。

公开(公告)号：US20080265305A1

公开(公告)日：2008-10-30

申请号：US12145681

申请日：2008-06-25

申请人： Yue-Song He ,  Len Mei

发明人： Yue-Song He ,  Len Mei

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7854 ,  H01L29/7881

摘要： A floating gate memory cell's channel region (104) is at least partially located in a fin-like protrusion (110P) of a semiconductor substrate. The floating gate's top surface may come down along at least two sides of the protrusion to a level below the top (110P-T) of the protrusion. The control gate's bottom surface may also comes down to a level below the top of the protrusion. The floating gate's bottom surface may comes down to a level below the top of the protrusion by at least 50% of the protrusion's height. The dielectric (120) separating the floating gate from the protrusion can be at least as thick at the top of the protrusion as at a level (L2) which is below the top of the protrusion by at least 50% of the protrusion's height. A very narrow fin or other narrow feature in memory and non-memory integrated circuits can be formed by providing a first layer (320) and then forming spacers (330) from a second layer without photolithography on sidewalls of features made from the first layer. The narrow fin or other feature are then formed without further photolithography in areas between the adjacent spacers. More particularly, a third layer (340) is formed in these areas, and the first layer and the spacers are removed selectively to the third layer. The third layer is used as a mask to form the narrow features.

公开(公告)号：US07414281B1

公开(公告)日：2008-08-19

申请号：US10658936

申请日：2003-09-09

申请人： Richard M. Fastow ,  Yue-Song He ,  Zhigang Wang

发明人： Richard M. Fastow ,  Yue-Song He ,  Zhigang Wang

IPC分类号： H01L29/76

CPC分类号： H01L29/513 ,  H01L29/7881

摘要： A flash memory cell and a method of forming the same are described. The flash memory cell may include a substrate having a source and a drain, a gate element, and a dielectric layer between the substrate and the gate element. The dielectric layer includes a dielectric material having a dielectric constant that is greater than that of silicon dioxide.

摘要翻译： 描述闪存单元及其形成方法。 闪速存储单元可以包括在衬底和栅极元件之间具有源极和漏极的衬底，栅极元件和介电层。 电介质层包括介电常数大于二氧化硅的电介质材料。

公开(公告)号：US06825526B1

公开(公告)日：2004-11-30

申请号：US10759809

申请日：2004-01-16

申请人： Yue-Song He ,  Nian Yang ,  Zhigang Wang

发明人： Yue-Song He ,  Nian Yang ,  Zhigang Wang

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： According to one exemplary embodiment, a memory array comprises first and second isolation regions situated in a substrate, where the first and second isolation regions are separated by a separation distance. The memory array further comprises a trench situated between the first and second isolation regions, where the trench defines trench sidewalls and a trench bottom in the substrate. The memory array further comprises a tunnel oxide layer situated between the first and second isolation regions, where the tunnel oxide layer is situated on the trench sidewalls and the trench bottom. According to this embodiment, the memory array further comprises a channel region situated underneath the tunnel oxide layer and extending along the trench sidewalls and the trench bottom, where the channel region has an effective channel width, where the effective channel width increases as a height of the trench sidewalls increases.

摘要翻译： 根据一个示例性实施例，存储器阵列包括位于衬底中的第一和第二隔离区域，其中第一和第二隔离区域被分离距离。 存储器阵列还包括位于第一和第二隔离区之间的沟槽，其中沟槽限定衬底中的沟槽侧壁和沟底。 存储器阵列还包括位于第一和第二隔离区之间的隧道氧化物层，其中隧道氧化物层位于沟槽侧壁和沟槽底部。 根据该实施例，存储器阵列还包括位于隧道氧化物层下方并沿着沟槽侧壁和沟槽底部延伸的沟道区，其中沟道区具有有效沟道宽度，其中有效沟道宽度随着 沟槽侧壁增加。

公开(公告)号：US06541338B2

公开(公告)日：2003-04-01

申请号：US09917182

申请日：2001-07-30

申请人： Zhigang Wang ,  Yue-Song He ,  Richard Fastow

发明人： Zhigang Wang ,  Yue-Song He ,  Richard Fastow

IPC分类号： H01L218247

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A method of forming flash memory EEPROM devices having a low energy source implant and a high-energy VSS connection implant such that the intrinsic source defect density is reduced and the VSs resistance is low. The source regions are implanted with a low energy, low dosage dopant ions and the VSS regions are implanted with a high energy, high dosage dopant ions.

摘要翻译： 一种形成具有低能量源注入和高能量VSS连接注入的闪存EEPROM器件的方法，使得本征源缺陷密度降低并且VSs电阻低。 源区域注入低能量，低剂量掺杂剂离子，VSS区域注入高能量，高剂量掺杂剂离子。

公开(公告)号：US6027973A

公开(公告)日：2000-02-22

申请号：US987526

申请日：1997-12-09

申请人： Yue-Song He

发明人： Yue-Song He

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： A NAND type flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of memory cells which each include a floating gate for storing charge when the cell is programmed. Select lines are used to control programming, reading and erasing of the cells. The floating gates and the select line are integrally formed from a first polysilicon layer (POLY 1). A contact area of the select line which is used to make external connection through a vertical interconnect (via) is made thicker than the floating gates to avoid punchthrough of the contact area during a dry etching step which is used to form the via. The POLY 1 layer is first formed to an initial thickness, and a silicon nitride mask layer is formed over the POLY 1 layer. The portion of the silicon nitride layer over the contact area is protected with photoresist, and the remaining area of the silicon nitride layer is etched away. A predetermined surface thickness of the POLY 1 layer is oxidized to form silicon dioxide, and the silicon dioxide is etched away using an etchant which has a low, preferably zero etch rate for polysilicon, such that the thickness of the polysilicon layer except in the contact area which is protected by the silicon nitride mask layer is reduced. The thinned polysilicon layer is then patterned to form the select lines and the floating gates.

摘要翻译： NAND型闪存电可擦除可编程只读存储器（闪存EEPROM）包括存储器单元阵列，每个存储单元包括用于在单元被编程时存储电荷的浮动栅极。 选择行用于控制单元格的编程，读取和擦除。 浮置栅极和选择线由第一多晶硅层（POLY 1）整体形成。 用于通过垂直互连（通孔）进行外部连接的选择线的接触区域比浮动栅极厚，以避免在用于形成通孔的干蚀刻步骤期间接触区域的穿透。 首先将POLY 1层形成初始厚度，在POLY 1层上形成氮化硅掩模层。 接触区域上的氮化硅层的部分被光致抗蚀剂保护，并且蚀刻掉氮化硅层的剩余面积。 POLY 1层的预定表面厚度被氧化以形成二氧化硅，并且使用对多晶硅具有低的，优选为零蚀刻速率的蚀刻剂来蚀刻掉二氧化硅，使得除了接触之外的多晶硅层的厚度 被氮化硅掩模层保护的区域减少。 然后将薄化的多晶硅层图案化以形成选择线和浮动栅极。

公开(公告)号：US20100323511A1

公开(公告)日：2010-12-23

申请号：US12872192

申请日：2010-08-31

申请人： Yue-Song He ,  Len Mei

发明人： Yue-Song He ,  Len Mei

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/42344

摘要： Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.

摘要翻译： 非易失性存储单元中的电荷俘获电介质（160）从控制栅极的边缘和/或从衬底隔离区域的边缘凹陷。 凹入的几何形状用于减少或消除电荷难以擦除的区域中的电荷捕获。

公开(公告)号：US20090159957A1

公开(公告)日：2009-06-25

申请号：US11961183

申请日：2007-12-20

申请人： Yue-Song He ,  Len Mei

发明人： Yue-Song He ,  Len Mei

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/42344

摘要： Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.

摘要翻译： 非易失性存储单元中的电荷俘获电介质（160）从控制栅极的边缘和/或从衬底隔离区域的边缘凹陷。 凹入的几何形状用于减少或消除电荷难以擦除的区域中的电荷捕获。

公开(公告)号：US07283398B1

公开(公告)日：2007-10-16

申请号：US10838962

申请日：2004-05-04

申请人： Yue-Song He ,  Richard Fastow ,  Takao Akaogi ,  Wing Leung ,  Zhigang Wang

发明人： Yue-Song He ,  Richard Fastow ,  Takao Akaogi ,  Wing Leung ,  Zhigang Wang

IPC分类号： G11C16/06

CPC分类号： G11C16/0466 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3477

摘要： The present invention provides a method for determining program and erase states in flash memory devices. Specifically, one embodiment of the present invention discloses a method for minimizing false detection of states in an array of non-volatile floating gate memory cells. A plurality of word lines are arranged in a plurality of rows. A plurality of bit lines are arranged in a plurality of columns. The method begins by determining a selected bit line that is associated with a column of memory cells. Then, the method continues by biasing a group of word lines at a negative voltage. The group of word lines are electrically coupled to the associated memory cells. The application of negative voltage to the group of word lines limits leakage current contributions from the associated memory cells in the column of memory cells when performing a verify operation.

摘要翻译： 本发明提供一种用于确定闪存设备中的程序和擦除状态的方法。 具体地，本发明的一个实施例公开了一种用于使非易失性浮动栅极存储单元的阵列中的状态的错误检测最小化的方法。 多个字线被布置成多行。 多个位线被布置在多个列中。 该方法通过确定与一列存储器单元相关联的所选位线开始。 然后，该方法通过在一个负电压下偏置一组字线来继续。 字线组电耦合到相关联的存储器单元。 当执行验证操作时，将负电压施加到字线组限制了来自存储器单元列中的相关联存储器单元的泄漏电流贡献。