公开(公告)号：US20110080792A1

公开(公告)日：2011-04-07

申请号：US12575137

申请日：2009-10-07

Applicant: Hagop Nazarian ,  Richard Fastow

Inventor： Hagop Nazarian ,  Richard Fastow

IPC: G11C16/04 ,  G11C7/00

CPC classification number: G11C16/0491 ,  G11C5/06 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/10

Abstract: Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the parallel bitline architecture enables very fast read times comparable with drain-based tunneling processes, achieving a combination of fast program, erase and read times far better than conventional non-volatile memories.

Abstract translation: 本文描述了提供非易失性存储器架构和存储器处理技术的新组合。 作为示例，公开了与基于通道的处理技术相结合的并行位线半导体架构。 基于通道的处理技术提供快速的程序/擦除时间，相对较高的密度和良好的可扩展性。 此外，并行位线架构可实现与基于漏极的隧道工艺相当的非常快的读取时间，实现了比常规非易失性存储器更好的快速程序，擦除和读取时间的组合。

公开(公告)号：US06737703B1

公开(公告)日：2004-05-18

申请号：US10095512

申请日：2002-03-12

Applicant: Richard Fastow ,  Sameer Haddad ,  Yu Sun

Inventor： Richard Fastow ,  Sameer Haddad ,  Yu Sun

IPC: H01L218247

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: In a memory device, a substrate has a plurality of source/drain regions in the substrate. Between the source/drain regions are trenches filled with oxide. Individual bit lines in the form of conductive regions are provided in the substrate, each bit line being under and running along the oxide in a trench. Each bit line connects to source/drain regions by means of connecting conductive regions extending from that bit line to source/drain regions.

Abstract translation: 在存储器件中，衬底在衬底中具有多个源极/漏极区域。 在源极/漏极区之间是填充有氧化物的沟槽。 导电区域形式的单个位线设置在衬底中，每个位线沿着沟槽中的氧化物在下面并且沿着其延伸。 每个位线通过将从该位线延伸的导电区域连接到源极/漏极区域而连接到源极/漏极区域。

公开(公告)号：US06541338B2

公开(公告)日：2003-04-01

申请号：US09917182

申请日：2001-07-30

Applicant: Zhigang Wang ,  Yue-Song He ,  Richard Fastow

Inventor： Zhigang Wang ,  Yue-Song He ,  Richard Fastow

IPC: H01L218247

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A method of forming flash memory EEPROM devices having a low energy source implant and a high-energy VSS connection implant such that the intrinsic source defect density is reduced and the VSs resistance is low. The source regions are implanted with a low energy, low dosage dopant ions and the VSS regions are implanted with a high energy, high dosage dopant ions.

Abstract translation: 一种形成具有低能量源注入和高能量VSS连接注入的闪存EEPROM器件的方法，使得本征源缺陷密度降低并且VSs电阻低。 源区域注入低能量，低剂量掺杂剂离子，VSS区域注入高能量，高剂量掺杂剂离子。

公开(公告)号：US06252803B1

公开(公告)日：2001-06-26

申请号：US09692881

申请日：2000-10-23

Applicant: Richard Fastow ,  Sameer S. Haddad ,  Lee E. Cleveland ,  Chi Chang

Inventor： Richard Fastow ,  Sameer S. Haddad ,  Lee E. Cleveland ,  Chi Chang

IPC: G11C1616

CPC classification number: G11C16/16

Abstract: A method of erasing a flash electrically-erasable programmable read-only memory (EEPROM) device is provided which includes a plurality of memory cells. An erase pulse is applied to the plurality of memory cells. The plurality of memory cells is overerase verified and an overerase correction pulse is applied to the bitline to which the overerased memory cell is attached. This cycle is repeated until all cells verify as not being overerased. The plurality of memory cells is erase verified and another erase pulse is applied to the memory cells if there are undererased memory cells and the memory cells are again erase verified. This cycle is repeated until all cells verify as not being undererased. After erase verify is completed, the plurality of memory cells is soft program verified and a soft programming pulse is applied to the those memory cells in the plurality of memory cells which have a threshold voltage below a pre-defined minimum value. This cycle is repeated until all of those memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value are brought above the pre-defined minimum value. The erase method is considered to be finished when there are no memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value.

Abstract translation: 提供擦除闪存电可擦除可编程只读存储器（EEPROM）设备的方法，其包括多个存储器单元。 擦除脉冲被施加到多个存储单元。 多个存储器单元被过度验证，并且过高修正脉冲被施加到被过度存储的存储单元附着的位线。 重复此循环，直到所有的单元格都被验证为不被过高。 多个存储器单元被擦除验证，并且如果存在未存储的存储器单元并且存储器单元再次被擦除验证，则另一个擦除脉冲被施加到存储器单元。 重复此循环，直到所有单元格都被验证为不被忽略。 在擦除验证完成之后，多个存储器单元被软件程序验证，并且将软编程脉冲施加到具有低于预定义最小值的阈值电压的多个存储单元中的那些存储单元。 重复该循环，直到具有低于预定义最小值的阈值电压的多个存储器单元中的所有那些存储器单元高于预定义的最小值。 当多个存储单元中没有存储单元的阈值电压低于预先定义的最小值时，擦除方法被认为是完成的。

公开(公告)号：US06207978B1

公开(公告)日：2001-03-27

申请号：US09516472

申请日：2000-03-01

Applicant: Richard Fastow

Inventor： Richard Fastow

IPC: H01L29812

CPC classification number: H01L29/7883 ,  H01L29/1054 ,  H01L29/66825

Abstract: A flash memory device and a method to manufacture the flash memory device. The flash memory device includes a modulation-doped heterostructure formed in a semiconductor substrate, a layer of tunnel oxide, a floating gate, a layer of dielectric, a control gate and source and drain regions formed in the substrate.

Abstract translation: 闪速存储器件和制造闪存器件的方法。 闪速存储器件包括形成在半导体衬底中的调制掺杂异质结构，隧道氧化物层，浮栅，介电层，控制栅极和形成在衬底中的源极和漏极区。

公开(公告)号：US20190043591A1

公开(公告)日：2019-02-07

申请号：US15836124

申请日：2017-12-08

Applicant: RICHARD FASTOW ,  XIN SUN ,  UDAY CHANDRASEKHAR ,  KRISHNA K. PARAT ,  CAMILA JARAMILLO ,  PURVAL S. SULE ,  ALIASGAR S. MADRASWALA

Inventor： RICHARD FASTOW ,  XIN SUN ,  UDAY CHANDRASEKHAR ,  KRISHNA K. PARAT ,  CAMILA JARAMILLO ,  PURVAL S. SULE ,  ALIASGAR S. MADRASWALA

IPC: G11C16/28 ,  G11C16/16 ,  G11C11/4074 ,  G11C16/34

Abstract: A controller for a NAND memory array is presented. In embodiments, the controller may include circuitry to provide bias voltages to a NAND memory array that includes two or more decks of memory cells, and an output interface coupled to the circuitry and to wordlines (WLs) of the memory array. In embodiments, the circuitry, in a deck erase operation may: apply a first set of bias voltages via the output interface to active WLs of at least a first deck of the two or more decks of memory cells to be erased; and apply a second set of bias voltages via the output interface to active WLs of at least a second deck of the two or more decks of memory cells not to be erased, wherein the first set of bias voltages is lower than the second set of bias voltages.

公开(公告)号：US08681558B2

公开(公告)日：2014-03-25

申请号：US12575137

申请日：2009-10-07

Applicant: Hagop Nazarian ,  Richard Fastow

Inventor： Hagop Nazarian ,  Richard Fastow

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/0491 ,  G11C5/06 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/10

Abstract: Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the parallel bitline architecture enables very fast read times comparable with drain-based tunneling processes, achieving a combination of fast program, erase and read times far better than conventional non-volatile memories.

Abstract translation: 本文描述了提供非易失性存储器架构和存储器处理技术的新组合。 作为示例，公开了与基于通道的处理技术相结合的并行位线半导体架构。 基于通道的处理技术提供快速的程序/擦除时间，相对较高的密度和良好的可扩展性。 此外，并行位线架构可实现与基于漏极的隧道工艺相当的非常快的读取时间，实现了比常规非易失性存储器更好的快速程序，擦除和读取时间的组合。

公开(公告)号：US08279674B2

公开(公告)日：2012-10-02

申请号：US12824352

申请日：2010-06-28

Applicant: Richard Fastow ,  Hagop Nazarian ,  Lei Xue

Inventor： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

IPC: G11C11/34 ,  G11C16/04 ,  G11C5/06

CPC classification number: G11C16/0483 ,  G11C5/063 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573

Abstract: Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture.

Abstract translation: 本文描述了提供与常规串行阵列存储器相比实现高读取速度的串行阵列存储器晶体管架构。 作为示例，串行阵列存储器可以连接到并且可以驱动小电容通过晶体管的栅极电压，以便于感测串行阵列的存储器晶体管。 传输晶体管调制相邻金属位线处的电流或电压，其可用于感测存储器晶体管的编程或擦除状态。 由于传输晶体管的小电容，串行阵列的读延迟可以显着低于常规串行阵列存储器（例如，NAND存储器）。 此外，描述了用于形成包括离散传输晶体管的串行阵列存储器的放大器区域的各种机制，以促进串行阵列存储晶体管架构的有效制造。

公开(公告)号：US07283398B1

公开(公告)日：2007-10-16

申请号：US10838962

申请日：2004-05-04

Applicant: Yue-Song He ,  Richard Fastow ,  Takao Akaogi ,  Wing Leung ,  Zhigang Wang

Inventor： Yue-Song He ,  Richard Fastow ,  Takao Akaogi ,  Wing Leung ,  Zhigang Wang

IPC: G11C16/06

CPC classification number: G11C16/0466 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3477

Abstract: The present invention provides a method for determining program and erase states in flash memory devices. Specifically, one embodiment of the present invention discloses a method for minimizing false detection of states in an array of non-volatile floating gate memory cells. A plurality of word lines are arranged in a plurality of rows. A plurality of bit lines are arranged in a plurality of columns. The method begins by determining a selected bit line that is associated with a column of memory cells. Then, the method continues by biasing a group of word lines at a negative voltage. The group of word lines are electrically coupled to the associated memory cells. The application of negative voltage to the group of word lines limits leakage current contributions from the associated memory cells in the column of memory cells when performing a verify operation.

Abstract translation: 本发明提供一种用于确定闪存设备中的程序和擦除状态的方法。 具体地，本发明的一个实施例公开了一种用于使非易失性浮动栅极存储单元的阵列中的状态的错误检测最小化的方法。 多个字线被布置成多行。 多个位线被布置在多个列中。 该方法通过确定与一列存储器单元相关联的所选位线开始。 然后，该方法通过在一个负电压下偏置一组字线来继续。 字线组电耦合到相关联的存储器单元。 当执行验证操作时，将负电压施加到字线组限制了来自存储器单元列中的相关联存储器单元的泄漏电流贡献。

公开(公告)号：US20070002620A1

公开(公告)日：2007-01-04

申请号：US11170950

申请日：2005-06-30

Applicant: Richard Fastow ,  Krishna Parat ,  Johnny Javanifard

Inventor： Richard Fastow ,  Krishna Parat ,  Johnny Javanifard

IPC: G11C16/04

CPC classification number: G11C16/16 ,  G11C16/344 ,  G11C16/3445

Abstract: A memory array includes a coupled controller for controlling the writing to, reading from and erasure of memory cells and blocks of memory cells within the memory array. The controller is operable during an erase process to determine and reduce odd/even wordline offset. The controller operates on separately settable odd/even wordline erase voltages, which are adjusted to affect offset.

Abstract translation: 存储器阵列包括耦合的控制器，用于控制对存储器单元的存储器单元和存储器单元的块的写入，读取和擦除。 控制器在擦除过程中可操作以确定和减少奇数/偶数字线偏移。 控制器可以单独设置的奇/偶字线擦除电压进行操作，这些电压被调整以影响偏移。