Image processing apparatus that can generate coded data applicable to progressive reproduction
    22.
    发明申请
    Image processing apparatus that can generate coded data applicable to progressive reproduction 有权
    可以生成适用于逐行再现的编码数据的图像处理装置

    公开(公告)号:US20050084169A1

    公开(公告)日:2005-04-21

    申请号:US10953758

    申请日:2004-09-29

    申请人: Yukio Kadowaki

    发明人: Yukio Kadowaki

    摘要: An image processing apparatus divides data related to an image into bit-planes and performs a coding process on data of each of the bit-planes. The image processing apparatus includes a multi-layer generation part that divides codes obtained by the coding process into a plurality of layers sequentially from the codes corresponding to higher bit-planes such that the amount of the codes of each of the layers is equal to or less than a predetermined value. A code generation part generates coded data in units of the codes divided into the layers by the multi-layer generation part.

    摘要翻译: 图像处理装置将与图像相关的数据分割成位平面,并对每个位平面的数据执行编码处理。 图像处理装置包括:多层生成部,其通过对应于较高位平面的代码顺序地将通过编码处理获得的代码分割成多个层,使得每个层的代码量等于或 小于预定值。 代码生成部生成由多层生成部分分割成层的代码的编码数据。

    Digital signal processing device
    23.
    发明授权
    Digital signal processing device 失效
    数字信号处理装置

    公开(公告)号:US5794067A

    公开(公告)日:1998-08-11

    申请号:US536134

    申请日:1995-09-29

    申请人: Yukio Kadowaki

    发明人: Yukio Kadowaki

    摘要: A digital signal processing device includes: a processing unit which performs basic operations, the processing unit transmitting an instruction signal including an instruction described by an instruction code when a special-function operation is performed; a plurality of functional blocks, each connected to the processing unit, which perform special-function operations in accordance with the instruction signal; a bus which interconnects the processing unit and the respective functional blocks to transmit a data signal and the instruction signal; and a block selecting unit, responsive to a status signal, which transmits an enable signal to at least one of the functional blocks to select the above-mentioned at least one of the functional blocks, so that the selected functional block is enabled to receive the instruction signal via the bus and to perform at least one of the special-function operations in accordance with the instruction signal, thereby generating processed data which is transmitted back to the processing unit.

    摘要翻译: 数字信号处理装置包括:执行基本操作的处理单元,当执行特殊功能操作时,处理单元发送包括由指令代码描述的指令的指令信号; 多个功能块,各自连接到处理单元,其根据指令信号进行特殊功能操作; 将处理单元和各功能块互连的总线,发送数据信号和指示信号; 以及块选择单元,响应于状态信号,所述状态信号向至少一个功能块发送使能信号以选择上述至少一个功能块,使得所选择的功能块能够接收 通过总线指示信号,并根据指令信号执行至少一项特殊功能操作,从而产生被传送回处理单元的处理后的数据。

    Serial communication device, method thereof and communication system using the same
    25.
    发明授权
    Serial communication device, method thereof and communication system using the same 有权
    串行通信装置及其通信系统

    公开(公告)号:US07720089B2

    公开(公告)日:2010-05-18

    申请号:US10562436

    申请日:2005-06-28

    申请人: Yukio Kadowaki

    发明人: Yukio Kadowaki

    IPC分类号: H04B7/212

    CPC分类号: H04L5/16 H04L7/0008

    摘要: A compact serial communication device is disclosed that is formed from simplified circuits on a master side and a slave side and does not need a synchronous signal and a switching unit for switching transmission and reception operations, and is able to reduce load of the slave side. The master transmission/reception circuit outputs a serial data signal DATA to a transmission path with the serial data signal DATA being generated by superposing a low level superposition pulse on a clock signal, when the clock signal is at the high level, according to an output data signal to be output to the slave transmission/reception circuits; the slave transmission/reception circuits superposes a high level superposition pulse on the serial data signal DATA input from the transmission path according to an output data signal to be output to the master transmission/reception circuit when the clock signal is at the low level.

    摘要翻译: 公开了一种紧凑型串行通信设备,其由主侧和从侧的简化电路形成,并且不需要同步信号和用于切换发送和接收操作的切换单元,并且能够减少从侧的负载。 根据输出,主发送/接收电路将串行数据信号DATA输出到传输路径,其中当时钟信号处于高电平时,通过在时钟信号上叠加低电平叠加脉冲来产生串行数据信号DATA 数据信号输出到从发送/接收电路; 从机发送/接收电路根据输出数据信号,在从时钟信号处于低电平时输出到主发送/接收电路的传输路径输入的串行数据信号DATA叠加高电平叠加脉冲。

    Image processing device, image processing method, and image reading method
    26.
    发明授权
    Image processing device, image processing method, and image reading method 有权
    图像处理装置,图像处理方法和图像读取方法

    公开(公告)号:US07349579B2

    公开(公告)日:2008-03-25

    申请号:US10247896

    申请日:2002-09-20

    IPC分类号: G06K9/36 G06K9/46

    摘要: The present invention provides an image processing device, an image processing method, and an image reading method, by which encoded data can be easily generated from sub-sampled image data, without a complicated circuit or an increase in the data amount. A one-dimensional wavelet transform in a predetermined direction is omitted in stage 1, where components 1 and 2 of input image data have been sub-sampled. When coefficient data generated through such a two-dimensional wavelet transform are to be encoded, sub-bands that are not contained in the coefficient data in comparison with the coefficient data of a component 0 should be considered to have been truncated.

    摘要翻译: 本发明提供了一种图像处理装置,图像处理方法以及图像读取方法,可以不经过复杂的电路或数据量的增加而从副采样图像数据容易地生成编码数据。 在阶段1中省略了一个预定方向的一维小波变换,其中输入图像数据的分量1和2已被二次采样。 当对通过这样的二维小波变换生成的系数数据进行编码时,与系统数据相比,不包含在系数数据中的子带应被认为是截断的。

    Serial communication device, method thereof and communication system using the same
    28.
    发明申请
    Serial communication device, method thereof and communication system using the same 有权
    串行通信装置及其通信系统

    公开(公告)号:US20060187969A1

    公开(公告)日:2006-08-24

    申请号:US10562436

    申请日:2005-06-28

    申请人: Yukio Kadowaki

    发明人: Yukio Kadowaki

    IPC分类号: H04J3/06

    CPC分类号: H04L5/16 H04L7/0008

    摘要: A compact serial communication device is disclosed that is formed from simplified circuits on a master side and a slave side and does not need a synchronous signal and a switching unit for switching transmission and reception operations, and is able to reduce load of the slave side. The master transmission/reception circuit outputs a serial data signal DATA to a transmission path with the serial data signal DATA being generated by superposing a low level superposition pulse on a clock signal, when the clock signal is at the high level, according to an output data signal to be output to the slave transmission/reception circuits; the slave transmission/reception circuits superposes a high level superposition pulse on the serial data signal DATA input from the transmission path according to an output data signal to be output to the master transmission/reception circuit when the clock signal is at the low level.

    摘要翻译: 公开了一种紧凑型串行通信装置,其由主侧和从侧的简化电路形成,不需要同步信号和用于切换发送和接收操作的切换单元,并且能够减少从侧的负载。 根据输出,主发送/接收电路将串行数据信号DATA输出到传输路径,其中当时钟信号处于高电平时,通过在时钟信号上叠加低电平叠加脉冲来产生串行数据信号DATA 数据信号输出到从发送/接收电路; 根据输出数据信号,从机发送/接收电路将高电平叠加脉冲叠加在从传输路径输入的串行数据信号DATA上,以在时钟信号为低电平时输出到主发送/接收电路。

    Multiple pulse series generating device and method applicable to random
pulse series generating apparatus
    29.
    发明授权
    Multiple pulse series generating device and method applicable to random pulse series generating apparatus 失效
    多脉冲串发生装置及方法适用于随机脉冲串发生装置

    公开(公告)号:US5611021A

    公开(公告)日:1997-03-11

    申请号:US430689

    申请日:1995-04-27

    CPC分类号: H03K3/84

    摘要: A linear feedback shift register comprises a plurality of flip-flop devices, wherein the linear shift register is constituted so as to provide a plurality of pseudo-random pulse series in parallel. A data providing device performs a calculation on the plurality of pseudo-random pulse series so as to provide a plurality of output pulse series in parallel, wherein each of the plurality of output pulse series has the pulse generating probability different from the pulse generating probability of each of the other pulse series of the plurality of output pulse series.

    摘要翻译: 线性反馈移位寄存器包括多个触发器装置,其中线性移位寄存器构成为并行提供多个伪随机脉冲序列。 数据提供装置对多个伪随机脉冲序列执行计算,以并行提供多个输出脉冲序列,其中多个输出脉冲序列中的每一个具有与脉冲发生概率不同的脉冲产生概率 每个其他脉冲串的多个输出脉冲串。

    Flip-flop circuit in a scanning test apparatus
    30.
    发明授权
    Flip-flop circuit in a scanning test apparatus 失效
    扫描测试装置中的触发器电路

    公开(公告)号:US5517108A

    公开(公告)日:1996-05-14

    申请号:US82096

    申请日:1993-06-24

    申请人: Yukio Kadowaki

    发明人: Yukio Kadowaki

    CPC分类号: G01R31/318552

    摘要: A scanning circuit apparatus for test includes a first selecting circuit for selecting one of a normal data signal and a scanning data signal by a first control signal and for transmitting the selected data signal, a second selecting circuit for selecting one of a normal clock signal and a scanning clock signal by a second control signal and for transmitting a first clock signal based on the selected clock signal, a data transferring clock signal generating circuit for generating a second clock signal based on a clock signal for transferring data, a latch section connected to the first selecting circuit, the second selecting circuit and the clock signal generating device for receiving the selected data signal, the first clock signal and the second clock signal and for outputting a signal corresponding to the selected data signal and defined by a logical product of the first clock signal and the second clock signal.

    摘要翻译: 一种用于测试的扫描电路装置包括:第一选择电路,用于通过第一控制信号选择正常数据信号和扫描数据信号之一,并用于发送所选数据信号;第二选择电路,用于选择正常时钟信号和 通过第二控制信号的扫描时钟信号,并且用于基于所选择的时钟信号发送第一时钟信号;数据传送时钟信号发生电路,用于基于用于传送数据的时钟信号产生第二时钟信号;锁存部分,连接到 第一选择电路,第二选择电路和用于接收所选数据信号的时钟信号产生装置,第一时钟信号和第二时钟信号,并用于输出与所选数据信号相对应的信号,并由 第一时钟信号和第二时钟信号。