Systems and methods for on ear detection of headsets

    公开(公告)号:US11810544B2

    公开(公告)日:2023-11-07

    申请号:US17705974

    申请日:2022-03-28

    Inventor: Brenton Steele

    Abstract: Embodiments generally relate to a signal processing device for on ear detection for a headset. The device comprises a first microphone input for receiving a microphone signal from a first microphone, the first microphone being configured to be positioned inside an ear of a user when the user is wearing the headset; a second microphone input for receiving a microphone signal from a second microphone, the second microphone being configured to be positioned outside the ear of the user when the user is wearing the headset; and a processor. The processor is configured to receive microphone signals from each of the first microphone input and the second microphone input; pass the microphone signals through a first filter to remove low frequency components, producing first filtered microphone signals; combine the first filtered microphone signals to determine a first on ear status metric; pass the microphone signals through a second filter to remove high frequency components, producing second filtered microphone signals; combine the second filtered microphone signals to determine a second on ear status metric; and combine the first on ear status metric with the second on ear status metric to determine the on ear status of the headset.

    Class D amplifier circuit
    23.
    发明授权

    公开(公告)号:US11804813B2

    公开(公告)日:2023-10-31

    申请号:US17386287

    申请日:2021-07-27

    Abstract: This application relates to Class D amplifier circuits. A modulator controls a Class D output stage based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block, which may comprise an ADC, generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input of a signal selector block. The input signal may be received at a second input of the signal selector block. The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block.

    Driver circuits
    24.
    发明授权

    公开(公告)号:US11792569B2

    公开(公告)日:2023-10-17

    申请号:US18101816

    申请日:2023-01-26

    CPC classification number: H04R3/00 H03K17/687 H03F3/217

    Abstract: The application describes a switched driver (401) for outputting a drive signal at an output node (402) to drive a load such as a transducer. The driver receives respective high-side and low-side voltages (VinH, VinL) defining an input voltage at first and second input nodes and has connections for first and second capacitors (403H, 403L). A network of switching paths is configured such that each of the first and second capacitors can be selectively charged to the input voltage, the first input node can be selectively coupled to a first node (N1) by a path that include or bypass the first capacitor, and the second input node can be selectively coupled to a second node (N2) by a path that includes or bypasses the second capacitor. The output node (402) can be switched between two switching voltages at the first or second nodes. The driver is selectively operable in different operating modes, where the switching voltages are different in each of said modes.

    Artificial neural networks
    25.
    发明授权

    公开(公告)号:US11790220B2

    公开(公告)日:2023-10-17

    申请号:US18089020

    申请日:2022-12-27

    Inventor: John Paul Lesso

    CPC classification number: G06N3/065 G06F7/16 G06N3/04

    Abstract: The present disclosure relates to a neuron for an artificial neural network. The neuron comprises a dot product engine operative to: receive a set of weights; receive a set of data inputs based on a set of input data signals; and calculate the dot product of the set of data inputs and the set of weights to generate a dot product engine output. The neuron further comprises an activation function module arranged to apply an activation function to a signal indicative of the dot product engine output to generate a neuron output; and gain control circuitry. The gain control circuitry is operative to control: an input gain applied to the input data signals to generate the set of data inputs; and an output gain applied to the dot product engine output or by the activation function module. The output gain is selected to compensate for the applied input gain.

    Biometric authentication
    27.
    发明授权

    公开(公告)号:US11748462B2

    公开(公告)日:2023-09-05

    申请号:US17113917

    申请日:2020-12-07

    Inventor: John Paul Lesso

    CPC classification number: G06F21/32 G10L15/1815 G10L15/22 G10L15/30

    Abstract: A method for authenticating a user of an electronic device is disclosed. The method comprises: responsive to detection of a trigger event indicative of a user interaction with the electronic device, generating an audio probe signal to play through an audio transducer of the electronic device; receiving a first audio signal comprising a response of the user's ear to the audio probe signal; receiving a second audio signal comprising speech of the user; and applying an ear biometric algorithm to the first audio signal and a voice biometric algorithm to the second audio signal to authenticate the user as an authorised user.

    Zero-crossing management in Class-D audio amplifiers

    公开(公告)号:US11722107B2

    公开(公告)日:2023-08-08

    申请号:US17589047

    申请日:2022-01-31

    CPC classification number: H03F3/2178 H03F1/26 H03F3/187 H03F2200/03

    Abstract: Class-D amplifier circuits provide operation with low-distortion zero crossings outside of a unipolar power supply voltage range. The amplifiers include a first H-bridge driver circuit and a second H-bridge driver circuit. The class-D amplifier circuits also include a control circuit having an input for receiving an input signal to be reproduced by the class-D amplifier circuit. The control circuit has outputs coupled to inputs of the first and second H-bridge drivers, and includes one or more modulators. The control circuit selects between actively operating a selected one of the driver circuits or both, according to the signal to be reproduced, while setting an unselected driver circuit to turn either a high-side switch or a low-side switch of the unselected one of the first driver circuit or the second driver circuit fully on for at least some cycles of the one or more modulators.

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