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公开(公告)号：US20240235541A1
公开(公告)日：2024-07-11
申请号：US18536319
申请日：2023-12-12
发明人： YA-HSUAN SUNG
IPC分类号： H03K17/082 , H03K17/06
CPC分类号： H03K17/0822 , H03K17/063
摘要： A switch circuit that has input and output terminals and a control terminal includes first to fourth transistors, a resistor, and a pull-low circuit. The first transistor has first and terminals. The second transistor has third and fourth terminals. The third transistor has fifth and sixth terminals. The fourth transistor has seventh and eighth terminals. The first to fourth transistors have first to fourth control terminals, respectively. The resistor has ninth and tenth terminals. The control terminal is coupled to the first and fourth control terminals. The first and third terminals are coupled to the input terminal. The second and sixth terminals are coupled to the output terminal. The fourth terminal is coupled to the fifth and ninth terminals. The seventh terminal is coupled to the tenth terminal and the second and third control terminals. The eighth terminal is coupled to a reference voltage.
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公开(公告)号：US12032020B2
公开(公告)日：2024-07-09
申请号：US18069479
申请日：2022-12-21
发明人： Chun-Yi Kuo , Ying-Yen Chen , Hsiao Tzu Liu
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/318552 , G01R31/318541
摘要： The present application discloses a calibration data generation circuit and an associated method. The calibration data generation circuit includes: a first delay unit, having a first delay amount; and a first scan path, including: a first scan flip-flop, including: a scan data input terminal; a clock input terminal, arranged for receiving a clock signal; and an output terminal; and a second scan flip-flop, including: a scan data input terminal, coupled to the output terminal of the first scan flip-flop; a clock input terminal, arranged for receiving a delayed clock signal formed by the clock signal passing through the first delay unit; and an output terminal; wherein when the calibration data generation circuit operates, the first scan flip-flop and the second scan flip-flop are configured in a scan shift mode.
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公开(公告)号：US20240214015A1
公开(公告)日：2024-06-27
申请号：US18537856
申请日：2023-12-13
发明人： MING-CHUN HSU , CHIN-CHUN HUANG
IPC分类号： H04B1/04
CPC分类号： H04B1/0475
摘要： A signal predistortion circuit configuration includes a digital predistortion (DPD) circuit, a first transceiver, and a second transceiver, and can reduce the influence of poor signal path insulation when performing a DPD training. During the DPD training, the DPD circuit transmits a training signal through a first signal path to adjust first predistortion parameters, and transmits a training signal through a second signal path to adjust second predistortion parameters. The first signal path includes: a transmitting circuit and an analog-front-end circuit of the first transceiver, a receiving analog circuit and a switch circuit of the second transceiver, and a switch circuit and an analog-to-digital converter (ADC) of the first transceiver. The second signal path includes: a transmitting circuit and an analog-front-end circuit of the second transceiver, a receiving analog circuit and the switch circuit of the first transceiver, and the switch circuit and an ADC of the second transceiver.
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公开(公告)号：US20240213242A1
公开(公告)日：2024-06-27
申请号：US18329589
申请日：2023-06-06
发明人： Tzu-Chieh WEI
IPC分类号： H01L27/088 , H01L23/482 , H01L23/485 , H01L27/02 , H01L29/423
CPC分类号： H01L27/0886 , H01L23/4824 , H01L23/485 , H01L27/0207 , H01L29/4238
摘要： An integrated circuit is provided and includes multiple first conductive segments, multiple second conductive segments, multiple third conductive segments, multiple fourth conductive segments, a first conductive line, and a second conductive line. The plurality of first conductive segments and the third conductive segments are arranged between multiple first gates, and the second conductive segments and the fourth conductive segments are arranged between multiple second gates. The first conductive line transmits a drain/source signal and is coupled to the first conductive segments and the second conductive segments. The second conductive line transmits a source/drain signal and is coupled to the third conductive segments and the fourth conductive segments. The plurality of third conductive segments and the fourth conductive segments are mirrored symmetrically with respect to the second conductive line in a plan view.
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公开(公告)号：US12008253B2
公开(公告)日：2024-06-11
申请号：US17966002
申请日：2022-10-14
发明人： Ya-Kun Cai , Hong Chang , Wen-Juan Ni
CPC分类号： G06F3/064 , G06F3/0607 , G06F8/65 , G06F3/0673
摘要： An embedded system includes a host controller circuit and a microcontroller circuit. The host controller circuit is configured to access a storage device to obtain an address of a first firmware file in the storage device. The microcontroller circuit is configured to determine whether a memory circuit is being accessed by other circuits, in which the memory circuit includes memory blocks. If the memory circuit is not being accessed by the other circuits, the microcontroller circuit is further to control the host controller circuit to write the first firmware file to a first block of the memory blocks according to the address.
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26.发明公开公开(公告)号：US20240178847A1
公开(公告)日：2024-05-30
申请号：US18510710
申请日：2023-11-16
发明人： MING-JHE DU , Ming-Hsuan Tsai , Chun-I Yeh , Yu-Chong Yen
摘要： The present disclosure discloses a media communication apparatus having built-in signal synchronization mechanism. A local clock generation circuit generates a reference clock signal and a media clock signal. A time calibration circuit performs time calibration process with an external apparatus to generate time calibration information to further calibrate the reference clock signal and the media clock signal accordingly to generate a calibrated reference clock signal and a calibrated media clock signal on a standard time domain. A media clock processing circuit generates a sampling signal according to the calibrated media clock signal. A signal processing circuit generates time related information according to the calibrated reference clock signal to process an input media signal according to the time related information and the sampling signal and generate an output media signal.
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公开(公告)号：US11995797B2
公开(公告)日：2024-05-28
申请号：US17972195
申请日：2022-10-24
发明人： Kang-Yu Liu , Chia-Wei Yu
IPC分类号： G06T3/4046 , G06N3/045 , G06T3/4053
CPC分类号： G06T3/4053 , G06N3/045
摘要： A super resolution image generating device capable of processing an image flexibly includes a scaling-up circuit, a front-end circuit, a first branch circuit, a second branch circuit, and an arithmetic circuit. The scaling-up circuit scales up the image to generate an enlarged image including N pixel values. The front-end circuit extracts features of the image to generate a front-end feature map. The first branch circuit extracts features of the front-end feature map to generate a first feature map, and scales up the first feature map to generate N first values. The second branch circuit processes the front-end feature map to generate a second feature map, scales up the second feature map to generate N second values, and processes the N second values to generate N processed values. The arithmetic circuit combines the N pixel values, the N first values, and the N processed values to generate a super resolution image.
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公开(公告)号：US11994961B2
公开(公告)日：2024-05-28
申请号：US17536138
申请日：2021-11-29
发明人： Chia-Wei Yu , Chun-Hsing Hsieh
CPC分类号： G06F11/162 , G06F11/1004 , G09G3/006 , G09G5/022 , G09G2360/127 , G09G2360/18
摘要： An image display system includes a display device, a second memory circuit, and an image processor circuit. The display device includes a panel and a first memory circuit, in which the first memory circuit is configured to store first predetermined data for controlling the panel. The second memory circuit is configured to store second predetermined data. The image processor circuit is configured to read first part data in the first predetermined data and second part data in the second predetermined data and compare the first part data with the second part data. If the first part data is identical to the second part data, the image processor circuit is further configured to output a driving signal according to the second predetermined data to control the panel to start displaying an image.
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29.发明授权公开(公告)号：US11991011B2
公开(公告)日：2024-05-21
申请号：US17644341
申请日：2021-12-15
发明人： Bing Chen , Tao Cui , Mingxu Wang , Zheng-Bei Xing
CPC分类号： H04L12/10 , G06F13/385 , G06F13/4221
摘要： A power supply device including a register circuit, an internal control circuit, and a storage circuit is disclosed. The register circuit includes a first sub-register circuit and a second sub-register circuit. The first sub-register circuit and the second sub-register circuit are configured to take turns to temporarily store a data transmitted form an external control circuit. The internal control circuit is coupled to the register circuit, and the internal control circuit is configured to obtain the data temporarily stored in the first sub-register circuit and the second sub-register circuit. The storage circuit is coupled to the internal control circuit, and the storage circuit is configured to obtain the data from the internal control circuit and to store the data.
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30.发明公开公开(公告)号：US20240163231A1
公开(公告)日：2024-05-16
申请号：US18481222
申请日：2023-10-04
发明人： Ying-Sheng TSAI , Jen-Che TSAI , Shiao-Yang WU
IPC分类号： H04L49/901 , H04L49/9005
CPC分类号： H04L49/901 , H04L49/9005
摘要： An electronic apparatus includes a processing unit, a buffer memory and a buffer manager. The buffer memory includes some packet buffer slots. Each of the packet buffer slots aligns to a packet size. The buffer manager includes a cache for registering available pointers. Each of the available pointers is configured to mark a start address of one of the packet buffer slots. The buffer manager is configured to monitor an available pointer count of the available pointers. When the processing unit transmits an allocation request to the buffer manager and the available count is enough, the buffer manager obtains one available pointer from the cache and integrates the one available pointer and the available pointer count into an allocation response, which is sent to the processing unit.
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