公开(公告)号：US20240037042A1

公开(公告)日：2024-02-01

申请号：US18340291

申请日：2023-06-23

Applicant: QUALCOMM Incorporated

Inventor： Ajay Kumar Rathee ,  Conrado Blasco

IPC: G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F12/1009 ,  G06F2212/1021

Abstract: Using retired pages history for instruction translation lookaside buffer (TLB) prefetching in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device is provided. The processor-based device comprises a history-based instruction TLB prefetcher (HTP) circuit configured to determine that a first instruction of a first page has been retired. The HTP circuit is further configured to determine a first page virtual address (VA) of the first page. The HTP circuit is also configured to determine that the first page VA differs from a value of a last retired page VA indicator of the HTP circuit. The HTP circuit is additionally configured to, responsive to determining that the first page VA differs from the value of the last retired page VA indicator of the HTP circuit, store the first page VA as the value of the last retired page VA indicator.

公开(公告)号：US11868273B2

公开(公告)日：2024-01-09

申请号：US16458007

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： David M. Durham

IPC: G06F12/14 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/1408 ,  G06F12/1009 ,  G06F12/1425 ,  G06F12/1027

Abstract: Embodiments are directed to memory protection with hidden inline metadata to indicate data type and capabilities. An embodiment of a processor includes a processor core and cache memory. The processor core is to implant hidden inline metadata in one or more cachelines for the cache memory, the hidden inline metadata hidden at a linear address level, hidden from software, the hidden inline metadata to indicate data type or capabilities for the associated data stored on the same cacheline.

公开(公告)号：US11841805B2

公开(公告)日：2023-12-12

申请号：US17877135

申请日：2022-07-29

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/123 ,  G06F9/30 ,  G06F12/1027 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F12/123 ,  G06F3/0619 ,  G06F3/0652 ,  G06F3/0658 ,  G06F3/0659 ,  G06F9/30043 ,  G06F12/0246 ,  G06F12/1027 ,  G06F3/0679

Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a host configured to generate and output a host command and a host address and to receive and store host map data, a controller configured to store map data, generate an internal command in response to the host command, and map the host address to an internal address based on the map data, and a memory device configured to perform an operation in response to the internal command and the internal address, wherein the controller is configured to load, when the map data corresponding to the host address is not stored in the controller, new map data into a map data storage area storing map data that is identical to the host map data.

公开(公告)号：US20230393989A1

公开(公告)日：2023-12-07

申请号：US18209967

申请日：2023-06-14

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F12/0895 ,  G06F12/0846 ,  G11C8/06 ,  G06F12/1027 ,  G06F12/0802

CPC classification number: G06F12/0895 ,  G06F12/0851 ,  G11C8/06 ,  G06F12/1027 ,  G06F12/0802 ,  G06F2212/1044

Abstract: A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory controller includes an interface that transfers the first data address and the first tag address for a first set of memory operations in the first and the second external memory arrays. The interface transfers the second data address and the second tag address for a second set of memory operations in the first and the second external memory arrays.

公开(公告)号：US20230393970A1

公开(公告)日：2023-12-07

申请号：US17900400

申请日：2022-08-31

Applicant: Bryan Hornung ,  Patrick Estep

Inventor： Bryan Hornung ,  Patrick Estep

IPC: G06F12/02 ,  G06F12/1027

CPC classification number: G06F12/0223 ,  G06F12/1027 ,  G06F2212/657

Abstract: Disclosed in some examples, are methods, systems, devices, and machine-readable mediums which solve the above problems using a global shared region of memory that combines memory segments from multiple CXL devices. Each memory segment is a same size and naturally aligned in its own physical address space. The global shared region is contiguous and naturally aligned in the virtual address space. By organizing this global shared region in this manner, a series of three tables may be used to quickly translate a virtual address in the global shared region to a physical address. This prevents TLB thrashing and improves performance of the computing system.

公开(公告)号：US20230385203A1

公开(公告)日：2023-11-30

申请号：US18101352

申请日：2023-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngseok KIM ,  Junbeom JANG ,  Seongmin JO

IPC: G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F12/1009

Abstract: Disclosed is an input output memory management unit (IOMMU) including a first memory device including a translation lookaside buffer (TLB), a second memory device including a translation group table, a plurality of translation request controllers, each of which is configured to perform an address translation operation, and an allocation controller. The allocation controller may be configured to receive a first request including a first page table identifier (ID), a first virtual page number, and a first page offset, looks up the TLB by using the first page table ID and the first virtual page number, look up the translation group table by using the first page table ID and the first virtual page number when a TLB miss for the first request occurs, and allocate a first translation request controller among the plurality of translation request controllers based on a translation group table miss for the first request.

公开(公告)号：US11829299B2

公开(公告)日：2023-11-28

申请号：US17819418

申请日：2022-08-12

Applicant: Intel Corporation

Inventor： David M. Durham ,  Michael LeMay ,  Men Long

IPC: G06F12/00 ,  G06F12/1027 ,  G06F12/14 ,  G06F9/30 ,  G06F12/1045 ,  G06F12/1081

CPC classification number: G06F12/1027 ,  G06F9/3005 ,  G06F12/1408 ,  G06F12/1475 ,  G06F12/1045 ,  G06F12/1081 ,  G06F2212/402 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/652 ,  G06F2212/657 ,  Y02D10/00

Abstract: Technologies for execute only transactional memory include a computing device with a processor and a memory. The processor includes an instruction translation lookaside buffer (iTLB) and a data translation lookaside buffer (dTLB). In response to a page miss, the processor determines whether a page physical address is within an execute only transactional (XOT) range of the memory. If within the XOT range, the processor may populate the iTLB with the page physical address and prevent the dTLB from being populated with the page physical address. In response to an asynchronous change of control flow such as an interrupt, the processor determines whether a last iTLB translation is within the XOT range. If within the XOT range, the processor clears or otherwise secures the processor register state. The processor ensures that an XOT range starts execution at an authorized entry point. Other embodiments are described and claimed.

公开(公告)号：US11822475B2

公开(公告)日：2023-11-21

申请号：US17565594

申请日：2021-12-30

Applicant: IMEC VZW

Inventor： Manu Komalan Perumkunnil ,  Geert Van der Plas

IPC: G06F12/0815 ,  G06F12/1027 ,  G06F12/0875

CPC classification number: G06F12/0815 ,  G06F12/0875 ,  G06F12/1027

Abstract: Example embodiments relate to integrated circuits with 3D partitioning. One embodiment includes an integrated circuit. The integrated circuit includes a first integrated circuit layer that includes processing cores. The integrated circuit also includes a second integrated circuit layer that includes memory arrays associated with processing cores. Additionally, the integrated circuit includes an intermediate integrated circuit layer interconnected with the first and second integrated circuit layers and including memory control logic and interface circuitries for managing data exchange between the processing cores and the memory arrays.

公开(公告)号：US20230359481A1

公开(公告)日：2023-11-09

申请号：US18353018

申请日：2023-07-14

Applicant: Alipay (Hangzhou) Information Technology Co., Ltd.

Inventor： Jian Feng TAN ,  Ti Wei BIE ,  An Qi SHEN ,  Yong HE ,  Xin CHEN

IPC: G06F9/455 ,  G06F12/1027

CPC classification number: G06F9/45558 ,  G06F12/1027 ,  G06F2009/45583

Abstract: Implementations of the present specification provide a method and an apparatus for managing a TLB cache in a virtualization platform, where the virtualization platform runs a plurality of virtual machines, each virtual machine is allocated with a unique VPID, and all virtual logical processors in the virtual machine share the VPID; and a guest process running in the virtual machine is allocated with a PCID. An identifier field of a TLB entry in the TLB cache includes a VPID and a PCID. The method includes: in response to detecting a target guest process involving an invalid address mapping relationship, obtaining a current VPID and a current PCID corresponding to the target guest process; classifying the current PCID into an invalid PCID set corresponding to the current VPID, and selecting a PCID from an available PCID set of a target virtual machine as an updated PCID; and allocating the updated PCID to the target guest process, so an updated entry for the target guest process is recorded in a TLB cache, where an identifier field of the updated entry includes the updated PCID.

公开(公告)号：US11792293B2

公开(公告)日：2023-10-17

申请号：US17149752

申请日：2021-01-15

Applicant: BEIJING VOYAGER TECHNOLOGY CO., LTD.

Inventor： Fenglei Wang ,  Lingang Min

IPC: H04L67/568 ,  G06F9/54 ,  G06F9/48 ,  H04L67/1097 ,  G06F8/41 ,  G06F16/172 ,  G06F9/38 ,  G06F12/0862 ,  G06F12/1027 ,  H04W8/08 ,  G06F9/50

CPC classification number: H04L67/568 ,  G06F8/4442 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/4881 ,  G06F9/5038 ,  G06F9/542 ,  G06F12/0862 ,  G06F12/1027 ,  G06F16/172 ,  H04L67/1097 ,  H04W8/082 ,  G06F2209/482 ,  G06F2209/484

Abstract: A method for data processing is provided. The method may include: preprocessing initial data to obtain preprocessed data; storing the preprocessed data; receiving a data request made through an application, the data request including information relating to a storage path of contents that are requested; in response to the data request, determining, by a nearby proxy of a first proxy cluster in a first region, whether the contents requested in the data request are cached locally; and in response to a determination that the contents are cached locally, providing, by the nearby proxy, the contents to the application; or in response to a determination that the contents are not cached locally, acquiring, by the nearby proxy, the contents based on the information relating to the storage path of the contents; and providing, by the nearby proxy, the contents to the application.