公开(公告)号：US09287884B2

公开(公告)日：2016-03-15

申请号：US14185431

申请日：2014-02-20

Applicant: Microchip Technology Incorporated

Inventor： Bret Walters

IPC: H03L7/00 ,  H03L7/06 ,  G06F1/08 ,  H03K3/72 ,  H03K5/26 ,  H03K7/08 ,  H03K3/017 ,  H03L7/083 ,  H03K3/02

CPC classification number: H03L7/06 ,  G06F1/08 ,  H03K3/017 ,  H03K3/02 ,  H03K3/72 ,  H03K5/26 ,  H03K7/08 ,  H03L7/083

Abstract: A numerical controlled oscillator generating an output signal with a digital clock signal having a variable frequency is disclosed. The numerical oscillator is controlled by a programmable numerical value being subject to a transfer function and comprises a comparator configured to compare an output of the transfer function with a duty cycle register to generate the output signal.

Abstract translation: 公开了一种产生具有可变频率的数字时钟信号的输出信号的数控振荡器。 数字振荡器由可编程数值控制，受到传递函数的影响，并包括一个比较器，被配置为将传递函数的输出与占空比寄存器进行比较以产生输出信号。

公开(公告)号：US20140232474A1

公开(公告)日：2014-08-21

申请号：US14185431

申请日：2014-02-20

Applicant: Microchip Technology Incorporated

Inventor： Bret Walters

IPC: H03L7/06

CPC classification number: H03L7/06 ,  G06F1/08 ,  H03K3/017 ,  H03K3/02 ,  H03K3/72 ,  H03K5/26 ,  H03K7/08 ,  H03L7/083

Abstract: A numerical controlled oscillator generating an output signal with a digital clock signal having a variable frequency is disclosed. The numerical oscillator is controlled by a programmable numerical value being subject to a transfer function and comprises a comparator configured to compare an output of the transfer function with a duty cycle register to generate the output signal.

Abstract translation: 公开了一种产生具有可变频率的数字时钟信号的输出信号的数控振荡器。 数字振荡器由可编程数值控制，受到传递函数的影响，并包括一个比较器，被配置为将传递函数的输出与占空比寄存器进行比较以产生输出信号。

公开(公告)号：US08546979B2

公开(公告)日：2013-10-01

申请号：US12854561

申请日：2010-08-11

Applicant: Tammo Heeren ,  Fred Mercado

Inventor： Tammo Heeren ,  Fred Mercado

IPC: H03K3/64

CPC classification number: H03K3/72

Abstract: Pulse-generator circuits that permit independent control of pulse widths and the delays between successive pulses. In several embodiments, a pulse-generator subcircuit includes a transmission-line segment comprising first and second conductors, configured such that the first conductor is coupled to a first DC potential. The pulse-generator subcircuit further includes a terminating resistor coupled to a first end of the second conductor of the first transmission-line segment; this terminating resistor is matched to the characteristic impedance of the transmission-line segment. The pulse-generator subcircuit further includes first and second switches, controlled by first and second timing signals, respectively, and configured to selectively and independently connect respective first and second ends of the first conductor to a second DC potential. This second potential may be ground, in some embodiments, while the DC potential supplied to the pulse-generator subcircuit by the power-supply subcircuit may range from a very small voltage to voltages exceeding a kilovolt.

Abstract translation: 脉冲发生器电路允许独立控制脉冲宽度和连续脉冲之间的延迟。 在几个实施例中，脉冲发生器分支电路包括包括第一和第二导体的传输线段，其被配置为使得第一导体耦合到第一直流电位。 脉冲发生器分支电路还包括耦合到第一传输线段的第二导体的第一端的终端电阻器; 该终端电阻与传输线段的特性阻抗匹配。 脉冲发生器分支电路还包括分别由第一和第二定时信号控制的第一和第二开关，并且被配置为选择性地且独立地将第一导体的第一和第二端连接到第二直流电位。 在一些实施例中，该第二电位可以被研磨，而由电源子电路提供给脉冲发生器子电路的DC电压可以在非常小的电压到超过千伏的电压的范围。

公开(公告)号：US5416434A

公开(公告)日：1995-05-16

申请号：US26716

申请日：1993-03-05

Applicant: Steve Kootstra ,  Daniel J. Powers

Inventor： Steve Kootstra ,  Daniel J. Powers

IPC: H03K3/72 ,  H03K3/84

CPC classification number: H03K3/84 ,  H03K3/72

Abstract: Adaptive clock generator including a master clock. A control means detects the current operating mode and, in response, provides a corresponding integer output N. A programmable pulse generator provides an output clock signal comprising a "high" pulse having a predetermined width followed by a "low" pulse having a width of N master clock periods. A dithered clock signal may be provided when the control means provides an integer output N selected from a set of integer values. Preferably, N is selected in a random or pseudo-random manner.

Abstract translation: 自适应时钟发生器包括主时钟。 控制装置检测当前操作模式，并且作为响应提供对应的整数输出N.可编程脉冲发生器提供输出时钟信号，该输出时钟信号包括具有预定宽度的“高”脉冲，随后是“低”脉冲， N个主时钟周期。 当控制装置提供从一组整数值中选择的整数输出N时，可以提供颤动时钟信号。 优选地，以随机或伪随机方式选择N。

公开(公告)号：US4231104A

公开(公告)日：1980-10-28

申请号：US900189

申请日：1978-04-26

Applicant: Richard P. St. Clair

Inventor： Richard P. St. Clair

IPC: H03K5/00 ,  G01R31/3183 ,  G01R31/319 ,  H03K3/72 ,  H03K5/156 ,  H03K23/66 ,  G06F1/04 ,  G06M3/02

CPC classification number: G01R31/31922 ,  H03K23/665 ,  H03K3/72 ,  H03K5/156

Abstract: A signal generator featuring, in one aspect, a clock, a programmable means for counting signals from the clock and providing outputs at predetermined counts, a delay means for providing a timing signal after a predetermined delay following each output, the delay means having a resolution higher than that of the clock, and a programmable means for repeatedly incrementing the delay for successive timing signals to provide a timing signal period not necessarily an integer multiple of the period of the clock. Preferred embodiments feature an additional delay means for delaying the output of the clock to provide sequences of clock signals having the same period as the clock output but shifted in time so that each timing signal occurs simultaneously with a clock signal, an additional counter connected to be clocked by the clock signals and reset by the timing signals, and means controlled through the counter for generating timing edges with a resolution equal to that of the delay means.

Abstract translation: 一种信号发生器，在一个方面中具有时钟，用于对来自时钟的信号进行计数并以预定计数提供输出的可编程装置，用于在每个输出之后的预定延迟之后提供定时信号的延迟装置，延迟装置具有分辨率 高于时钟的可编程装置，以及用于重复递增连续定时信号的延迟的可编程装置，以提供不一定是时钟周期的整数倍的定时信号周期。 优选实施例具有附加延迟装置，用于延迟时钟的输出以提供具有与时钟输出相同周期但时间偏移的时钟信号序列，使得每个定时信号与时钟信号同时发生，附加计数器连接到 由时钟信号计时并由定时信号复位，以及通过计数器控制的装置，用于产生具有等于延迟装置的分辨率的定时边沿。

公开(公告)号：US3796961A

公开(公告)日：1974-03-12

申请号：US3796961D

申请日：1972-10-31

Applicant: INDUCTOSYN CORP

Inventor： TRIPP R

IPC: G05B19/4103 ,  G06F7/66 ,  G06F7/68 ,  H03K3/72 ,  H03K1/16

CPC classification number: H03K3/72 ,  G05B19/4103 ,  G05B2219/34034 ,  G05B2219/34132 ,  G05B2219/34179 ,  G05B2219/43139 ,  G05B2219/43158 ,  G05B2219/43187 ,  G06F7/66 ,  G06F7/68

Abstract: A pulse train conversion system includes a binary counter having a plurality of stages which store a count, the count being advanced in response to a clock pulse. The counter stages are respectively connected to counter inputs of a logic circuit, digital value inputs of the logic circuit being connected to registers having a plurality of stages. The logic circuit provides an output pulse in response to the output of a particular stage of the counter being false and outputs of all stages of the counter of lesser significance than the particular stage being true concurrently with a stage of the register, corresponding to the particular stage of the counter, being true.

公开(公告)号：US3736516A

公开(公告)日：1973-05-29

申请号：US3736516D

申请日：1971-06-14

Applicant: LORAIN PROD CORP

Inventor： ELLIS C

IPC: H02M7/48 ,  H03K3/72 ,  H03K5/20

CPC classification number: H03K3/72 ,  H02M7/48

Abstract: A circuit for providing an output pulse train which has a variable frequency when the circuit operates in a first mode and for providing an output pulse train which has a fixed, precise frequency when the circuit operates in a second mode. A fixed frequency pulse generator applies a pulse train having a fixed frequency to one input of a pulse frequency modifying circuit. A variable frequency pulse generator applies a pulse train having a variable frequency to another input of the pulse frequency modifying circuit. When the latter circuit operates in its first mode, the state of the voltage at the circuit output is controlled in accordance with both the fixed and variable frequency input pulse trains and the output pulse train reflects the algebraic sum thereof. When, however, the circuit operates in its second mode, the effect of the variable frequency input pulse train is suppressed and the output frequency is controlled solely in accordance with the frequency of the fixed frequency pulse generator.

Abstract translation: 一种用于提供输出脉冲序列的电路，当电路以第一模式工作时，具有可变频率，并且当电路在第二模式下工作时提供具有固定的精确频率的输出脉冲串。 固定频率脉冲发生器对脉冲频率修正电路的一个输入端施加具有固定频率的脉冲串。 可变频率脉冲发生器将具有可变频率的脉冲串施加到脉冲频率修正电路的另一个输入。 当后一电路在其第一模式下工作时，根据固定频率输入脉冲串和可变频率输入脉冲串来控制电路输出端的电压状态，并且输出脉冲串反映其代数和。 然而，当电路工作在第二模式时，可以抑制可变频率输入脉冲串的影响，并且仅根据固定频率脉冲发生器的频率来控制输出频率。

公开(公告)号：US3659226A

公开(公告)日：1972-04-25

申请号：US3659226D

申请日：1970-05-11

Applicant: SITS SOC IT TELECOM SIEMENS

Inventor： ANGELERI EMANUELE ,  BALUGANI FABIO

IPC: H03K3/72 ,  H04L27/12

CPC classification number: H04L27/122 ,  H03K3/72

Abstract: Two pulse trains with harmonically related repetition frequencies 1/To, 1/nTo are derived from an original square wave of cadence 2/To, the pulses of each train having the width To/4 of the square-wave pulses. With the aid of a second square wave of cadence To, produced by frequency halving from the original square wave, the two harmonically related pulse trains are additively or subtractively combined so as to produce an irregular pulse sequence with n + OR - 1 pulses in each period nTo of the lower-frequency train. A digital pulse counter derives from this irregular pulse sequency a low-frequency square wave converted, by filtration, into its fundamental sine wave whose frequency can thus be selectively varied, with only minor phase discontinuities, between three predetermined values related to one another as (n+1) : n : (n-1). In an alternative embodiment, the keying frequencies are related to the basic frequency as (2n+1) : 2n : (2n-1). The two pulse trains are generated by progressive frequency division, starting with the original square wave, and selective gating.

Abstract translation: 具有谐波相关重复频率1 / To，1 / nTo的两个脉冲序列从节奏2 / To的原始方波导出，每个列的脉冲具有方波脉冲的宽度To / 4。 借助于从原始方波频率减半产生的第二次方波，将两个谐波相关的脉冲串相加或相减组合，从而在每个周期内产生n +/- 1个脉冲的不规则脉冲序列 n至低频列车。 数字脉冲计数器从这种不规则脉冲序列中得出通过滤波转换成其基频正弦波的低频方波，其频率因此可以选择性地变化，只有较小的相位不连续性，在三个预定值之间相互关联为（ n + 1）：n：（n-1）。 在另一实施例中，键控频率与（2n + 1）：2n：（2n-1）的基本频率有关。 两个脉冲串是通过逐行分频产生的，从原始方波开始，选择性选通。

公开(公告)号：US3648180A

公开(公告)日：1972-03-07

申请号：US3648180D

申请日：1970-10-06

Applicant: BRITISH AIRCRAFT CORP LTD

Inventor： WOODCOCK TERENCE KEITH

IPC: H03K3/72 ,  H03K5/13 ,  H03K1/00

CPC classification number: H03K5/131 ,  H03K3/72

Abstract: The pulse generator is described in which a pair of storage registers are connected in parallel with one another and initially loaded such that a first of the registers has a substantially smaller unfilled capacity than the second register. A clock generator then feeds pulses equally to the two registers to progressively reduce the unfilled capacity of each register and when the first register has been filled a ''full'' signal is generated which causes immediate reloading of the first register to the same initial capacity. A logic circuit connected to selected bit outputs of the first register generates a pulse, or a pulse pattern, during the time taken to fill the first register and when the second register has been filled a second ''full'' signal inhibits the feeding of further clock pulses to the register. The total number of pulse cycles is therefore the ratio of the initially unfilled capacity of the second register to the unfilled capacity of the first register.

Abstract translation: 描述脉冲发生器，其中一对存储寄存器彼此并联连接并且初始加载，使得第一寄存器具有比第二寄存器基本上更小的未填充容量。 时钟发生器然后将脉冲同等地馈送到两个寄存器以逐渐减小每个寄存器的未填充容量，并且当第一寄存器已经被填充时，产生“完全”信号，这导致第一寄存器立即重新加载到相同的初始容量。 连接到第一寄存器的选定位输出的逻辑电路在填充第一寄存器的时间期间产生脉冲或脉冲模式，当第二寄存器已经被填充时，第二个“满”信号禁止进一步提供时钟 脉冲到寄存器。 因此，脉冲周期的总数是第二寄存器的初始未填充容量与第一寄存器的未填充容量的比率。

公开(公告)号：US20090115391A1

公开(公告)日：2009-05-07

申请号：US11935558

申请日：2007-11-06

Applicant: Chao-Hsuan Chuang ,  Cheng-Hsuan Fan ,  Hung-Che Chou ,  Ching-Hsiang Yang

Inventor： Chao-Hsuan Chuang ,  Cheng-Hsuan Fan ,  Hung-Che Chou ,  Ching-Hsiang Yang

IPC: G05F1/46 ,  H03K3/017

CPC classification number: H03K3/72

Abstract: The present invention discloses a load-dependent frequency jittering circuit, comprising: a load condition detection circuit for receiving a switching signal and generating an output according to a load condition; a number generator for receiving the output of the load condition detection circuit and generating a number; a digital to analog converter for converting the output of the number generator to an analog signal; and an oscillator for generating a jittered frequency according to the output of the digital to analog converter.

Abstract translation: 本发明公开了一种负载相关的频率抖动电路，包括：负载状态检测电路，用于接收开关信号并根据负载条件产生输出; 数字发生器，用于接收负载状态检测电路的输出并产生一个数字; 用于将数字发生器的输出转换为模拟信号的数模转换器; 以及用于根据数模转换器的输出产生抖动频率的振荡器。