公开(公告)号：US4680479A

公开(公告)日：1987-07-14

申请号：US759861

申请日：1985-07-29

Applicant: Sydney A. Alonso

Inventor： Sydney A. Alonso

IPC: G10H7/00 ,  H03K3/72 ,  H03K5/135 ,  H03K3/64

CPC classification number: G10H7/002 ,  H03K3/72

Abstract: A pulse generator for outputting a train of electric pulses with a controllably constant period (i.e., the reciprocal of pulse rate) between pulses of the pulse train. The generator includes electrical circuitry which produces an internal train of pulses some of whose periods vary an unacceptable amount from one another. Further, modifying circuitry is connected to receive each pulse of the internal train of pulses, the further circuitry being operable to modify the period of each pulse, when necessary, to an acceptable period with respect to the immediately preceding pulse. The modifying circuitry includes delay circuitry which in controlled, in part, by an input pulse to be processed and which is adapted to delay the input pulse by a delay time determined by lateness of the input pulse and to provide an output pulse (which is the output of the generator and which in combination with other pulses forms the output pulse train of the pulse generator) whose period is substantially equal to (or within acceptable variation from) other pulses of the train of electrical pulses.

Abstract translation: 一种脉冲发生器，用于以脉冲序列的脉冲之间的可控恒定周期（即，脉冲速率的倒数）输出一系列电脉冲。 发生器包括产生内部脉冲串的电路，其中一些脉冲周期彼此之间变化不可接受的量。 此外，连接修改电路以接收内部脉冲序列的每个脉冲，另外的电路可操作以在必要时将每个脉冲的周期修改到相对于紧接在前的脉冲的可接受的周期。 修改电路包括延迟电路，其部分地由待处理的输入脉冲控制，并且适于将输入脉冲延迟由输入脉冲的延迟确定的延迟时间，并提供输出脉冲（其为 发生器的输出并且与其他脉冲组合形成脉冲发生器的输出脉冲串），其周期基本上等于电脉冲串的其它脉冲的（或在可接受的变化范围内）。

公开(公告)号：US4209715A

公开(公告)日：1980-06-24

申请号：US859139

申请日：1977-12-09

Applicant: Kiyoshi Aoki

Inventor： Kiyoshi Aoki

IPC: H03K3/037 ,  H03K3/286 ,  H03K3/288 ,  H03K3/72 ,  H03K5/151 ,  H03K19/00 ,  H03K19/08 ,  H03K19/082 ,  H03K19/091 ,  H03K23/00 ,  H03K23/52 ,  H03K23/58 ,  H03K19/20 ,  H03K21/00

CPC classification number: H03K19/08 ,  H03K3/0372 ,  H03K3/286 ,  H03K3/288 ,  H03K3/72

Abstract: A logic circuit comprises four NAND or NOR gates. The first and second gates are cross-coupled and the third and fourth gates are also cross-coupled. The outputs of the first and second gates are coupled to the inputs of the third and fourth gates respectively. Complementary clock pulses are respectively supplied to the first and second gates and the third and fourth gates, and first and second logic inputs are applied to the inputs of the first and second gates, respectively.

Abstract translation: 逻辑电路包括四个NAND或NOR门。 第一和第二栅极是交叉耦合的，第三和第四栅极也是交叉耦合的。 第一和第二栅极的输出分别耦合到第三和第四栅极的输入端。 互补时钟脉冲分别提供给第一和第二栅极以及第三和第四栅极，并且第一和第二逻辑输入分别被施加到第一和第二栅极的输入端。

公开(公告)号：US3870963A

公开(公告)日：1975-03-11

申请号：US34499673

申请日：1973-03-26

Applicant: LOVESHAW CORP

Inventor： GROCE RAYMOND ,  KUSSEMAUL ERNEST A

IPC: H03K3/72 ,  H03K1/16

CPC classification number: H03K3/72

Abstract: A pulse generating system is disclosed wherein output pulses are provided at a rate decreasing or increasing from an initial rate with the passage of time. The output pulses are generated by a comparator responsive (1) to a first counter advanced in count by a constant rate pulse generator and (2) to a second counter which is presettable and is advanced or reduced in count from its preset count by a third counter which generates an output at each generation of a preselected number of pulses by the constant rate pulse generator.

Abstract translation: 公开了一种脉冲发生系统，其中以随时间推移的初始速率减小或增加的速率提供输出脉冲。 输出脉冲由比较器产生，响应于（1）到由恒定速率脉冲发生器计数的第一计数器，和（2）到可预置的第二计数器，并且从其预设计数开始计数第三计数器 计数器，其通过恒定速率脉冲发生器在每次产生预选数量的脉冲时产生输出。

公开(公告)号：US3439278A

公开(公告)日：1969-04-15

申请号：US3439278D

申请日：1967-01-24

Applicant: BELL TELEPHONE LABOR INC

Inventor： FARROW CECIL W

IPC: H03K3/72 ,  H03K21/08 ,  H03K23/70 ,  H03K21/00 ,  H03B19/00

CPC classification number: H03K21/08 ,  H03K3/72 ,  H03K23/70

公开(公告)号：US07728571B2

公开(公告)日：2010-06-01

申请号：US11935558

申请日：2007-11-06

Applicant: Chao-Hsuan Chuang ,  Cheng-Hsuan Fan ,  Hung-Che Chou ,  Ching-Hsiang Yang

Inventor： Chao-Hsuan Chuang ,  Cheng-Hsuan Fan ,  Hung-Che Chou ,  Ching-Hsiang Yang

IPC: G05F1/56

CPC classification number: H03K3/72

Abstract: The present invention discloses a load-dependent frequency jittering circuit, comprising: a load condition detection circuit for receiving a switching signal and generating an output according to a load condition; a number generator for receiving the output of the load condition detection circuit and generating a number; a digital to analog converter for converting the output of the number generator to an analog signal; and an oscillator for generating a jittered frequency according to the output of the digital to analog converter.

Abstract translation: 本发明公开了一种负载相关的频率抖动电路，包括：负载状态检测电路，用于接收开关信号并根据负载条件产生输出; 数字发生器，用于接收负载状态检测电路的输出并产生一个数字; 用于将数字发生器的输出转换为模拟信号的数模转换器; 以及用于根据数模转换器的输出产生抖动频率的振荡器。

公开(公告)号：US5877639A

公开(公告)日：1999-03-02

申请号：US887607

申请日：1997-07-03

Applicant: Michel Porcher ,  Stephane Chesnais ,  Jean Desuche

Inventor： Michel Porcher ,  Stephane Chesnais ,  Jean Desuche

IPC: H03K3/037 ,  H03K3/72 ,  H03B19/00

CPC classification number: H03K3/037 ,  H03K3/72

Abstract: A duration and frequency programmable electronic integrated pulse generator comprises an initialization circuit driven by a reference clock signal and an initialization/comparison signal and producing m initialization values, and a periodic count value coded on n bits. An address decoder module produces write-control bits, while a bits comparison matrix including n.times.m comparison cells each including a RAM and CAM memory cell write-addressable by the write-control bits. Each CAM cell stores a bit CAM.sub.ij of an initialization value and produces a complemented value CAM.sub.ij .sym.BL.sub.i , each RAM memory cell of address i, j produces a masking value M.sub.ij, and each comparison cell produces a value HIT.sub.ij =(CAM.sub.ij .sym.BL.sub.i)+M.sub.ij. All the cells of the same line of rank j are coupled by an OR function and produce, each output S.sub.j, a programmed pulse represented by the equation: ##EQU1## according to a harmonic periodic signal of the periodic count value.

Abstract translation: 持续时间和频率可编程电子集成脉冲发生器包括由参考时钟信号和初始化/比较信号驱动并产生m个初始化值的初始化电路以及以n位编码的周期性计数值。 地址解码器模块产生写入控制位，而包括n×m个比较单元的比特比较矩阵，每个比较单元包括可由写入控制位写入的RAM和CAM存储器单元。 每个CAM单元存储初始化值的位CAMij，并产生补码值+ E，ovs CAMij（+）BLi + EE，地址i的每个RAM存储单元j产生掩蔽值Mij，并且每个比较单元产生一个值 HITij = + E，ov（CAMij（+）BLi）+ EE + Mij。 等级j的相同行的所有单元通过OR功能耦合，并且根据周期性计数值的谐波周期信号，产生由以下等式表示的编程脉冲：每个输出Sj：。

公开(公告)号：US5540682A

公开(公告)日：1996-07-30

申请号：US372368

申请日：1995-01-13

Applicant: John A. Gardner ,  Geoffrey P. Taylor ,  Kevin A. Hebborn ,  Razi Adelinia

Inventor： John A. Gardner ,  Geoffrey P. Taylor ,  Kevin A. Hebborn ,  Razi Adelinia

IPC: A61B17/00 ,  A61B18/12 ,  G06F1/025 ,  H03K3/66 ,  H03K3/72 ,  H03K3/78 ,  A61B17/39

CPC classification number: G06F1/025 ,  A61B18/1206 ,  H03K3/66 ,  H03K3/72 ,  H03K3/78 ,  A61B2017/00154 ,  A61B2017/00172 ,  A61B2017/0019

Abstract: Electrosurgery apparatus has a processor that generates a data stream output representing the characteristics of the electrosurgery pulses to be generated. The data stream output comprises digitally-represented values indicative respectively of the width of each pulse, the duration of a first period during which pulses are to be generated, the duration of a second period during which pulses are not to be generated, the duration of a third period during which pulses are to be generated and the duration of a fourth period during which pulses are not to be generated. The data stream also includes digital instructions as to whether or not the electrosurgery output is to be cut only and whether it is to include spray coagulation. Three switch control units receive the data stream and provide outputs to three switching circuits, which provide two monopolar and one bipolar output. Each switching circuit includes a transformer connected to receive the outputs from the switch control units.

Abstract translation: 电外科设备具有产生表示要产生的电外科脉冲的特性的数据流输出的处理器。 数据流输出包括分别指示每个脉冲的宽度，要产生脉冲的第一周期的持续时间，不产生脉冲的第二周期的持续时间的数字表示的值， 将产生脉冲的第三周期和不产生脉冲的第四周期的持续时间。 数据流还包括关于电外科输出是否仅被切割以及是否包括喷雾凝结的数字指令。 三个开关控制单元接收数据流，并向三个开关电路提供输出，这三个开关电路提供两个单极和一个双极输出。 每个开关电路包括连接以接收来自开关控制单元的输出的变压器。

公开(公告)号：US4353123A

公开(公告)日：1982-10-05

申请号：US227995

申请日：1981-01-23

Applicant: Helmut Rost ,  Alfred Walz

Inventor： Helmut Rost ,  Alfred Walz

IPC: H04R3/00 ,  B06B1/02 ,  G01S7/524 ,  H03K3/017 ,  H03K3/72 ,  H04B11/00 ,  G01S7/52 ,  G10K11/00

CPC classification number: B06B1/0215 ,  H03K3/017 ,  H03K3/72

Abstract: It is the aim of the exemplary disclosure to create a simple system with as great a variability as possible wherein a pulse generator for each ultrasonic transducer element comprises a digital frequency control member for controlling the pulses to be fed to the transducer element and at which at least the pulse frequency (f.sub.s) can be selected by means of an input digital value (FW).

Abstract translation: 示例性公开的目的是创建具有尽可能大的可变性的简单系统，其中用于每个超声换能器元件的脉冲发生器包括数字频率控制构件，用于控制要馈送到换能器元件的脉冲， 最小脉冲频率（fs）可以通过输入数字值（FW）来选择。

公开(公告)号：US4229699A

公开(公告)日：1980-10-21

申请号：US908115

申请日：1978-05-22

Applicant: John M. Frissell

Inventor： John M. Frissell

IPC: G06F1/08 ,  H03K3/72 ,  H03K5/1252 ,  H03K1/17

CPC classification number: G06F1/08 ,  H03K3/72 ,  H03K5/1252

Abstract: A system for switching among a plurality of input clock signals to produce an output clock signal which avoids the presence of spurious signals during the process of switching from one to another of said plurality of input clock signals. When it is desired to switch from one input clock signal to a new input clock signal, clock output logic is inhibited from supplying any clock output signal for a selected time period, after which the newly selected input clock signal is supplied as the clock output signal. The time period is dependent on the clock pulse rate of the newly selected input clock signal and is sufficiently long to assure that no spurious signals will occur thereafter.

Abstract translation: 一种用于在多个输入时钟信号之间切换以产生输出时钟信号的系统，以避免在所述多个输入时钟信号中的一个切换到另一个的处理期间存在杂散信号。 当希望从一个输入时钟信号切换到新的输入时钟信号时，禁止时钟输出逻辑在所选择的时间周期内提供任何时钟输出信号，之后将新选择的输入时钟信号作为时钟输出信号 。 该时间段取决于新选择的输入时钟信号的时钟脉冲速率，并且足够长以确保其后不发生杂散信号。

公开(公告)号：US3928812A

公开(公告)日：1975-12-23

申请号：US41850773

申请日：1973-11-23

Applicant: XEROX CORP

Inventor： BATES ROGER D

IPC: H03K3/023 ,  H03K3/72 ,  H03B3/04

CPC classification number: H03K3/72 ,  H03K3/023

Abstract: An oscillator is provided to control the processing of binary digits. If such bits comprise video information which construct characters on a display monitor, then by varying the frequency of the oscillator the number of bits or pulses during visible portions of the scan time is controlled. The oscillator includes a register, counter, comparator logic, and speed correction circuitry. The oscillator itself has a disable input which in combination with the other elements provides an output signal that may also be started or stopped synchronously.

Abstract translation: 提供振荡器来控制二进制数字的处理。 如果这样的位包括在显示监视器上构造字符的视频信息，则通过改变振荡器的频率来控制扫描时间的可见部分期间的位数或脉冲数。 振荡器包括寄存器，计数器，比较器逻辑和速度校正电路。 振荡器本身具有禁止输入，其与其它元件组合提供也可以同步启动或停止的输出信号。