公开(公告)号：US11133072B2

公开(公告)日：2021-09-28

申请号：US16727599

申请日：2019-12-26

申请人： SK hynix Inc.

发明人： Young Jin Moon ,  Young Sub Yuk

IPC分类号： G11C7/02 ,  G11C16/30 ,  H03F3/45 ,  H03K5/24 ,  G11C29/50 ,  G11C16/04

摘要： A data storage apparatus includes storage, and a controller including an internal voltage trimming circuit and controlling the storage in response to a request from a host. The trimming circuit may include an integral circuit sampling a difference between a test voltage output by a device under test and a reference voltage, generating an integral signal by integrating a sampled signal, and including an offset cancellation unit cancelling an offset from the sampled signal, a comparison circuit generating a comparison signal by comparing the integral signal with the reference voltage, a code generation circuit receiving an initial trimming code and generating preliminary trimming codes by increasing or decreasing the initial trimming code in response to the comparison signal, and a code average signal generation circuit generating the final trimming code by averaging the preliminary trimming codes for a given time and provide the final trimming code to the storage.

公开(公告)号：US11107519B2

公开(公告)日：2021-08-31

申请号：US16601427

申请日：2019-10-14

申请人： Micron Technology, Inc.

发明人： Umberto Di Vincenzo ,  Lucia Di Martino

IPC分类号： G11C11/4091 ,  G11C11/4074 ,  G11C11/22 ,  G11C7/02

摘要： Techniques are described herein for mitigating parasitic signals induced by state transitions during an access operation of a selected memory cell in a memory device. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended coupling between various components of the memory device may occur during an access operation. To mitigate parasitic signals induced by the unintended coupling, the memory device may isolate the selected memory cell from a selected digit line during certain portions of the access operation. The memory device may isolate the selected memory cell when the plate transitions from a first voltage to a second, when the selected digit line transitions from a third voltage to a fourth voltage, or a combination thereof.

公开(公告)号：US11056163B2

公开(公告)日：2021-07-06

申请号：US16945793

申请日：2020-07-31

申请人： Arm Limited

发明人： El Mehdi Boujamaa ,  Cyrille Nicolas Dray

IPC分类号： G11C7/02 ,  G11C11/16 ,  H03F3/45

摘要： In a particular implementation, an apparatus including first and second bias circuits and an inner amplifier provides sense amplifier offset cancellation. The inner amplifier includes: first and second current generators configured to replicate respective first and second currents from the first and second bias circuits, first and second transistors configured to transform the first and second currents into voltage samples, and first and second capacitors configured to store the voltage samples. In a sampling phase, a sampling of the first and second currents may be performed in the inner amplifier, and further, in an amplification phase, an amplification of the stored voltage samples may also be performed in the inner amplifier.

公开(公告)号：US20210174863A1

公开(公告)日：2021-06-10

申请号：US17101574

申请日：2020-11-23

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC分类号： G11C11/4093 ,  G11C29/52 ,  G11C7/02 ,  G11C11/4096 ,  G06F11/10 ,  G11C29/04

摘要： Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US20210125657A1

公开(公告)日：2021-04-29

申请号：US17140753

申请日：2021-01-04

申请人： Apple Inc.

发明人： Sukalpa Biswas ,  Farid Nemati

IPC分类号： G11C11/402 ,  G11C5/06 ,  H01L23/00 ,  G11C5/04 ,  H01L25/10 ,  H01L25/065 ,  G11C5/02 ,  G11C7/02 ,  G11C11/406

摘要： In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g. an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.

公开(公告)号：US10978114B2

公开(公告)日：2021-04-13

申请号：US16462255

申请日：2018-10-31

申请人： ORDOS YUANSHENG OPTOELECTRONICS CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

发明人： Zhichong Wang

IPC分类号： G11C7/10 ,  G11C7/02 ,  G09G3/36 ,  G11C7/20 ,  G11C7/22

摘要： A shift register unit, a gate driving circuit, a display device and a driving method are disclosed. The shift register unit includes an input circuit, a first reset circuit, an output circuit, and a node control circuit. The input circuit is configured to control a level of a first node in response to an input signal; the first reset circuit is configured to reset the first node in response to the first reset signal; the output circuit is configured to output a driving signal to an output terminal under control of the level of the first node; and the node control circuit is configured to control a level of a second node in response to the driving signal.

公开(公告)号：US10943624B1

公开(公告)日：2021-03-09

申请号：US16541940

申请日：2019-08-15

申请人： Micron Technology, Inc.

发明人： Scott J. Derner

IPC分类号： G11C7/02 ,  G11C7/08 ,  G11C7/12 ,  G11C8/08

摘要： Apparatuses and methods can be related to countering noise at a memory array. Countering noise can include enable switches to connect third digit lines of the first array adjacent to the respective first digit lines to fourth digit lines of the second array adjacent to the reference digit lines such that the reference digit lines experience a same amount of digit line coupling noise as the first digit lines experience.

公开(公告)号：US20210050038A1

公开(公告)日：2021-02-18

申请号：US16541940

申请日：2019-08-15

申请人： Micron Technology, Inc.

发明人： Scott J. Derner

IPC分类号： G11C7/02 ,  G11C7/08 ,  G11C7/12 ,  G11C8/08

摘要： Apparatuses and methods can be related to countering noise at a memory array. Countering noise can include enable switches to connect third digit lines of the first array adjacent to the respective first digit lines to fourth digit lines of the second array adjacent to the reference digit lines such that the reference digit lines experience a same amount of digit line coupling noise as the first digit lines experience.

公开(公告)号：US10892259B2

公开(公告)日：2021-01-12

申请号：US16866723

申请日：2020-05-05

申请人： MICRON TECHNOLOGY, INC.

发明人： Michael Smith

IPC分类号： H01L27/02 ,  G11C16/04 ,  G11C16/16 ,  G11C16/22 ,  G11C7/02 ,  G11C16/08

摘要： Apparatus having an array of memory cells might include a first transistor having a control gate, a first source/drain connected to a first contact for connection to peripheral circuitry, and a second source/drain connected to a second contact for connection to a data line selectively connected to a respective set of strings of series-connected memory cells of the array of memory cells; and a second transistor having a control gate, a first source/drain connected to the second contact, and a second source/drain connected to a third contact for connection to a common source selectively connected to each string of series-connected memory cells of the respective set of strings of series-connected memory cells for the data line.

公开(公告)号：US10861787B1

公开(公告)日：2020-12-08

申请号：US16534120

申请日：2019-08-07

申请人： Micron Technology, Inc.

发明人： Mitsunari Sukekawa ,  Christopher J. Kawamura

IPC分类号： G11C11/4097 ,  G11C7/02 ,  H01L23/528 ,  G11C11/4091 ,  H01L27/108 ,  H01L25/18 ,  H01L23/58 ,  G11C7/18

摘要： Some embodiments include an integrated memory having a first bitline coupled with a first set of memory cells, and having a second bitline coupled with a second set of memory cells. The first and second bitlines are comparatively coupled through a sense amplifier. A first noise suppression line is adjacent to a region of the first bitline and extends parallel to the region of the first bitline. The first noise suppression line is electrically connected with one of the first and second bitlines and not with the other of the first and second bitlines. A second noise suppression line is adjacent to a region of the second bitline and extends parallel to the region of the second bitline. The second noise suppression line is electrically connected with the other of the first and second bitlines.