公开(公告)号：US20070085177A1

公开(公告)日：2007-04-19

申请号：US11545814

申请日：2006-10-10

Applicant: Kum-weng Loo ,  Chek-lim Kho ,  Jing-en Luan

Inventor： Kum-weng Loo ,  Chek-lim Kho ,  Jing-en Luan

IPC: H01L23/495 ,  H01L21/00

CPC classification number: H01L21/565 ,  H01L23/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and a molding material encapsulating the leadframe, the die, and the position member together to form the semiconductor package. The method for manufacturing a very thin semiconductor package includes disposing a first position member on one side of the die-attach pad of a leadframe, attaching a die onto the opposite side of the die-attach pad, optionally disposing a second position member on top of the die, electrically connecting the die to the lead terminals of the leadframe, and encapsulating the leadframe, the die, and the position member(s) together to form the very thin semiconductor package.

Abstract translation: 本公开提供了一种非常薄的半导体封装，其包括具有管芯附接焊盘和多个引线端子的引线框架，附接到管芯附接焊盘并且通过接合线电连接到引线端子的管芯，位置构件设置在 模具和/或管芯附接垫，以及将引线框，模具和位置构件封装在一起以形成半导体封装的成型材料。 用于制造非常薄的半导体封装的方法包括在引线框的管芯安装焊盘的一侧上设置第一位置构件，将管芯附接到管芯附接衬垫的相对侧上，可选地将第二位置构件设置在顶部 的模具，将管芯电连接到引线框架的引线端子，并将引线框架，模具和位置构件封装在一起以形成非常薄的半导体封装。

公开(公告)号：US20070081590A1

公开(公告)日：2007-04-12

申请号：US11525202

申请日：2006-09-21

Applicant: Kwong-Huang Goh ,  Lucas Hui

Inventor： Kwong-Huang Goh ,  Lucas Hui

IPC: H04N11/04 ,  H04N7/12

CPC classification number: H04N19/198 ,  H04N19/126 ,  H04N19/137 ,  H04N19/14 ,  H04N19/142 ,  H04N19/149 ,  H04N19/152 ,  H04N19/176 ,  H04N19/196 ,  H04N19/61

Abstract: A macro-block (MB) quantization reactivity compensation method for a video encoder is provided. The method calculates a reference picture quantization value based on a calculated picture complexity. This predicted reference quantization is combined with the bits-used reactive MB reference quantization value to determine the final MB reference quantization value. This MB reference quantization value is also made adaptive to the VBV buffer fullness, as well as to the predicted change of the current picture complexity. A video encoder and an article of manufacture that comprises computer readable program code for execution of the method are also provided.

Abstract translation: 提供了一种用于视频编码器的宏块（MB）量化反应性补偿方法。 该方法基于计算出的图像复杂度来计算参考图像量化值。 将该预测参考量化与使用位无效MB参考量化值组合以确定最终的MB参考量化值。 该MB参考量化值也适应于VBV缓冲器充满度以及当前图像复杂度的预测变化。 还提供了包括用于执行该方法的计算机可读程序代码的视频编码器和制品。

公开(公告)号：US07176983B2

公开(公告)日：2007-02-13

申请号：US10850963

申请日：2004-05-20

Applicant: Patricia Wei Yin Chiang ,  Lucas Y. W. Hui

Inventor： Patricia Wei Yin Chiang ,  Lucas Y. W. Hui

IPC: H04N5/21

CPC classification number: G06T5/003 ,  G06T5/20 ,  G06T7/13 ,  G06T2207/10016 ,  G06T2207/10024 ,  G06T2207/20012 ,  G06T2207/20192 ,  H04N5/142 ,  H04N5/21 ,  H04N9/77

Abstract: A processor for enhancing an input luminance signal including: a circuit for calculating a chroma edge value associated with the input luminance signal; a circuit for measuring a luminance gradient associated with the input luminance signal; a peaking filter for processing the input luminance signal; a gain adjustment circuit having a gain function that is adjustable relative to the calculated chroma edge value, the gain adjustment circuit being operable to adjust the magnitude of the output of the peaking filter wherein: in a first range of luminance gradients, the output is an attenuated version of the input; in a second range of luminance gradients the output is directly proportional to the input; in a third range of luminance gradients, the output is inversely proportional to the input; wherein the enhanced luminance signal is the sum of the input and output of the peaking filter.

Abstract translation: 一种用于增强输入亮度信号的处理器，包括：用于计算与输入亮度信号相关联的色度边缘值的电路; 用于测量与输入亮度信号相关联的亮度梯度的电路; 用于处理输入亮度信号的峰值滤波器; 所述增益调整电路具有相对于所计算的色度边缘值可调节的增益函数，所述增益调整电路可操作以调整所述峰值滤波器的输出的幅度，其中：在亮度梯度的第一范围内，所述输出为 衰减版本的输入; 在第二个亮度梯度范围内，输出与输入成正比; 在第三个亮度梯度范围内，输出与输入成反比; 其中增强的亮度信号是峰值滤波器的输入和输出之和。

公开(公告)号：US20060184861A1

公开(公告)日：2006-08-17

申请号：US11329382

申请日：2006-01-10

Applicant: Jianhua Sun ,  Sapna George

Inventor： Jianhua Sun ,  Sapna George

IPC: H03M13/00

CPC classification number: G10L21/04 ,  G10L19/005 ,  G10L25/18

Abstract: The present invention provides an audio streaming system and method for transmitting audio signals with high quality. The advantages of the present invention include easy implementation, computational efficiency, and provision of better audio quality. More particularly, the present invention provides a Multi-band Time Expansion algorithm for lost packet concealment. The Multi-band Time Expansion algorithm detects the number of continuously lost packets in an audio input signal and the correctly received packets on either side of the lost packets. Then the Multi-band Time Expansion algorithm time-expands the correctly received packets that may be from either one side or both sides of the lost packets, wherein the correctly received packets are stretched to cover the length of the lost packets. Finally the Multi-band Time Expansion algorithm overlap-adds the stretched packets so that the lost packets are concealed.

Abstract translation: 本发明提供了一种用于以高质量传输音频信号的音频流传输系统和方法。 本发明的优点包括容易实现，计算效率和提供更好的音频质量。 更具体地，本发明提供了一种用于丢包分组隐藏的多频带时间扩展算法。 多频段时间扩展算法检测音频输入信号中连续丢失分组的数量以及丢失分组任一侧的正确接收分组数。 然后，多频带时间扩展算法对可能来自丢失分组的一侧或两侧的正确接收的分组进行时间扩展，其中正确接收的分组被拉伸以覆盖丢失分组的长度。 最后，多频段时间扩展算法重叠 - 增加了扩展的数据包，使丢失的数据包被隐藏。

公开(公告)号：US20060159204A1

公开(公告)日：2006-07-20

申请号：US11333098

申请日：2006-01-17

Applicant: Muralidhar Karthik ,  Ser Oh

Inventor： Muralidhar Karthik ,  Ser Oh

IPC: H04L27/06

CPC classification number: H04L25/0204 ,  H04B1/7117 ,  H04B2201/70701 ,  H04L25/0224

Abstract: A method includes generating a plurality of noise-averaged channel estimates using noisy channel estimates. At least some of the noise-averaged channel estimates are generated using different averaging lengths. The method also includes selecting one of the averaging lengths based on the plurality of noise-averaged channel estimates. The step of selecting one of the averaging lengths may include subtracting the noise-averaged channel estimates from the noisy channel estimates to produce a plurality of noise-averaged differences and determining powers of the noise-averaged differences. The step of selecting one of the averaging lengths may also include determining total error powers associated with the different averaging lengths using the powers of the noise-averaged differences and selecting the averaging length corresponding to a lowest total error power.

Abstract translation: 一种方法包括使用噪声信道估计来生成多个噪声平均信道估计。 使用不同的平均长度生成噪声平均信道估计中的至少一些。 该方法还包括基于多个噪声平均信道估计来选择平均长度之一。 选择平均长度之一的步骤可以包括从噪声信道估计中减去噪声平均信道估计，以产生多个噪声平均差并确定噪声平均差的功率。 选择平均长度之一的步骤还可以包括使用噪声平均差的功率来确定与不同平均长度相关联的总误差功率，并且选择对应于最低总误差功率的平均长度。

公开(公告)号：US20060149540A1

公开(公告)日：2006-07-06

申请号：US11312005

申请日：2005-12-19

Applicant: Ravindra Singh ,  Anoop Krishna

Inventor： Ravindra Singh ,  Anoop Krishna

IPC: G10L19/12

CPC classification number: G10L19/107 ,  G10L2019/0013

Abstract: A method for performing a search of a codebook is provided. The codebook includes a plurality of tracks each having a plurality of even pulse positions. The method includes partitioning a codevector having a plurality of pulses into a first subset of pulses and a second subset of pulses. Each pulse is assignable to a pulse position in the codevector, and each pulse is associated with a shift bit for indicating an odd position. The method also includes performing a first search for determining a first set of possible pulse positions for the pulses in the codevector. The method further includes performing a second search for determining a second set of possible pulse positions for the pulses in the codevector. In addition, the method includes forming the codevector using the first and second sets of possible pulse positions.

公开(公告)号：US07061707B2

公开(公告)日：2006-06-13

申请号：US10955970

申请日：2004-09-30

Applicant: Hin Sing Fong ,  Ravi Shanker

Inventor： Hin Sing Fong ,  Ravi Shanker

IPC: G11B21/02

CPC classification number: G11B5/54 ,  G11B21/12

Abstract: A power loss retraction architecture is provided to retract the VCM arm of a hard disk drive upon power loss. The power loss retraction architecture is configurable to be able to use energy from different sources. The selected energy source is used efficiently by applying the energy only to the VCM retract arrangement, while isolating the energy source from other circuits that are not needed to accomplish the retraction operation.

Abstract translation: 功率损耗回缩结构被提供以在掉电时收回硬盘驱动器的VCM臂。 功率损耗回收架构可配置为能够使用来自不同来源的能量。 所选择的能量源通过将能量仅施加到VCM缩回装置而被有效地使用，同时将能源与不需要完成缩回操作的其他电路隔离。

公开(公告)号：US07016428B1

公开(公告)日：2006-03-21

申请号：US09831855

申请日：1998-11-14

Applicant: Pratima Pai ,  Godfrey Da Costa

Inventor： Pratima Pai ,  Godfrey Da Costa

IPC: H04L27/28 ,  H04L23/02

CPC classification number: H04L25/03828 ,  H04L25/4927

Abstract: A method and apparatus for efficient implementation of a frame-based trellis spectral shaping with a variable look-ahead depth that reduces memory and computational requirements that includes a data encoder for generating spectrally-shaped coded data according to a trellis coding system, a metric computation and trellis engine, and a processing circuit to apply a selected coding strategy to data frames to generate spectrally-shaped coded data form transmission.

Abstract translation: 一种用于有效实现具有可变预览深度的基于帧的网格光谱整形的方法和装置，其减少存储器和计算需求，所述存储器和计算要求包括根据网格编码系统产生频谱形状的编码数据的数据编码器，度量计算 和网格引擎，以及处理电路，以将选择的编码策略应用于数据帧，以产生频谱形状的编码数据形式传输。

公开(公告)号：US20060056552A1

公开(公告)日：2006-03-16

申请号：US10486168

申请日：2001-03-13

Applicant: Ser Oh ,  Chris Aldridge

Inventor： Ser Oh ,  Chris Aldridge

IPC: H04B1/10 ,  H04L7/00

CPC classification number: H04B1/7083 ,  H04B1/70735 ,  H04B1/708

Abstract: Two preferred embodiments provide slot synchronization of an initial cell search Two Finite Impulse Response (FIR) filters are used to correlate the synchronization codes transmitted in the downlink (forward link). A sign bit is taken after the first FIR to significantly reduce the hardware requirements for the second FIR, and thus the whole system. The correlated results from the second FIR can be further processed using two different algorithms. The first adds a square operation to the correlated results whilst the second takes the magnitude before passing to the next stage. Regardless of which algorithm is adopted, the results are accumulated (I and Q), instead of averaged, and stored in a memory location for each successive correlation over the same location in different slots. The physical-layer processor (PLP) then reads the accumulated results from the memory location and searches for the peak position corresponding to the slot boundary.

Abstract translation: 两个优选实施例提供了初始小区搜索的时隙同步。两个有限脉冲响应（FIR）滤波器用于使在下行链路（前向链路）中发送的同步码相关。 在第一个FIR之后采用符号位，以显着降低第二FIR的硬件要求，从而降低整个系统的硬件要求。 可以使用两种不同的算法进一步处理来自第二FIR的相关结果。 第一个对相关结果添加一个平方运算，而第二个运算在通过下一阶段之前的幅度。 无论采用哪种算法，结果都被累积（I和Q）而不是平均值，并且存储在不同时隙中相同位置上的每个连续相关的存储器位置。 物理层处理器（PLP）然后从存储器位置读取累积的结果，并搜索对应于时隙边界的峰值位置。

公开(公告)号：US07006100B2

公开(公告)日：2006-02-28

申请号：US10677629

申请日：2003-10-02

Applicant: Kah-Ho Phong ,  Lucas Y. W. Hui

Inventor： Kah-Ho Phong ,  Lucas Y. W. Hui

IPC: G09G5/36 ,  H04N7/12 ,  G06F13/00

CPC classification number: G06T1/60 ,  H04N19/433

Abstract: A cache memory system is used in a motion estimation system. The system includes: a first cache memory defined in terms of a first width and a first height, and a second cache memory defined in terms of a second width and a second height, wherein said second height is less than said first height, the cache memory system being operable in one of two modes: the first mode being characterized by banks of memory from the second cache memory being concatenated vertically such that their concatenated height is at least equal to the first height, and said concatenated banks being arranged to be appended to the width of the first cache memory to form a single contiguous address space; and the second mode being characterized by banks of memory from the first and second cache being stacked vertically, and being arranged to be addressed as two separate address spaces.

Abstract translation: 在运动估计系统中使用高速缓冲存储器系统。 该系统包括：根据第一宽度和第一高度定义的第一高速缓存存储器和根据第二宽度和第二高度定义的第二高速缓存存储器，其中所述第二高度小于所述第一高度，高速缓存 存储器系统可以以两种模式之一操作：第一模式的特征在于来自第二高速缓冲存储器的存储器组被垂直级联，使得它们的级联高度至少等于第一高度，并且所述级联存储体被布置为被附加 到第一个高速缓冲存储器的宽度以形成单个连续的地址空间; 并且第二模式的特征在于来自第一和第二高速缓存的存储器组是垂直堆叠的，并且被布置为被寻址为两个单独的地址空间。