公开(公告)号：US20240427974A1

公开(公告)日：2024-12-26

申请号：US18749348

申请日：2024-06-20

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik

IPC: G06F30/3308 ,  G06F30/333 ,  G06F119/06

Abstract: An example method for power emulation and estimation includes estimating a functional power consumption value associated with a memory system by determining: a scan-based power estimation, scan-based power measurement, a calibration factor from correlating the scan-based power estimation to the scan-based power measurement and a correlated functional power using the calibration factor. The calibration factor can be applied to a functional power estimation in order to achieve better accuracy.

公开(公告)号：US20240427657A1

公开(公告)日：2024-12-26

申请号：US18742798

申请日：2024-06-13

Applicant: Micron Technology, Inc.

Inventor： Jianping Tian ,  Da Hong

IPC: G06F11/07 ,  G06F9/4401

Abstract: Various embodiments described herein provide for bootloader failure analysis of a memory system using information regarding a failure of the bootloader, where the information is stored on the memory sub-system in response to detection of (e.g., stored at the time of) the failure. In particular, the stored information can comprise data that would be lost or otherwise inaccessible for subsequent diagnostic (e.g., debug) purposes, such as by a manufacturer of the memory sub-system. According to some embodiments, a memory sub-system is configured to save information regarding a failure of a bootloader, to one or more designated memory devices of the memory sub-system, such that diagnostic firmware (e.g., debug firmware) subsequently loaded and executed on the memory sub-system (e.g., by a manufacturer) can make use of the stored information to perform one or more diagnostic functions (e.g., debug functions) on the memory sub-system.

公开(公告)号：US20240427526A1

公开(公告)日：2024-12-26

申请号：US18830096

申请日：2024-09-10

Applicant: Micron Technology, Inc.

Inventor： Nicola Del Gatto ,  Emanuele Confalonieri ,  Paolo Amato ,  Patrick Estep ,  Stephen S. Pawlowski

IPC: G06F3/06 ,  G06F12/0864

Abstract: A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can include interface management circuitry coupled to a cache and a memory device. The memory controller can receive, by the interface management controller, a first signal indicative of data associated with a memory access request from a host. The memory controller can transmit a second signal indicative of the data to cache the data in a first location in the cache. The memory controller can transmit a third signal indicative of the data to cache the data in a second location in the cache.

公开(公告)号：US20240427507A1

公开(公告)日：2024-12-26

申请号：US18827515

申请日：2024-09-06

Applicant: Micron Technology, Inc.

Inventor： Sriteja Yamparala ,  Fulvio Rori ,  Marco Domenico Tiburzi ,  Walter Di Francesco ,  Chiara Cerafogli ,  Tawalin Opastrakoon

IPC: G06F3/06 ,  G06F1/08 ,  G06F1/28

Abstract: Various embodiments of the present disclosure relate to monitoring the integrity of power signals within memory systems. A method can include receiving a power signal at a memory component, and monitoring, via a power signal monitoring component of the memory component, an integrity characteristic of the power signal. Responsive to the integrity characteristic meeting a particular criteria, the method can include providing a status indication to a control component external to the memory component.

公开(公告)号：US20240425983A1

公开(公告)日：2024-12-26

申请号：US18680975

申请日：2024-05-31

Applicant: Micron Technology, Inc.

Inventor： Jean-Sebastien Materne Lehn ,  Francois H. Fabreguette ,  Timothy A. Quick

IPC: C23C16/455 ,  C23C16/24

Abstract: Methods, systems, and devices for methods for depositing silicon films by atomic layer deposition are described. For instance, a device may expose a base material (e.g., multiple stacks of materials) to a first precursor to form a silicon compound on the base material, the first precursor including a silicon amidinate. The device may react a second precursor with the silicon compound and may form a layer of silicon on the base material based on exposing the base material to the first precursor and reacting the second precursor with the silicon compound.

公开(公告)号：US12178041B2

公开(公告)日：2024-12-24

申请号：US18152647

申请日：2023-01-10

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Brett D. Lowe

IPC: H01L23/528 ,  G11C5/02 ,  G11C5/06 ,  H10B41/27 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, conductive contact structures in contact with the steps of the staircase structure, support pillar structures extending through the stack structure, and additional slot structures extending partially through the stack structure within one of the block structures, one of the additional slot structures extending between horizontally neighboring support pillar structures and closer to one of the horizontally neighboring support pillar structures than to an additional one of the horizontally neighboring support pillar structures. Related microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US12177167B2

公开(公告)日：2024-12-24

申请号：US17018256

申请日：2020-09-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Tamara Schmitz ,  Jeremy Chritz ,  Jaime Cummins

IPC: H04L5/14 ,  H04B1/525 ,  H04B7/026 ,  H04B7/06 ,  H04B7/08 ,  H04W4/40 ,  H04W4/70 ,  H04L5/00 ,  H04L25/02 ,  H04W76/14

Abstract: Examples described herein include apparatuses and methods for full duplex device-to-device cooperative communication. Example systems described herein may include self-interference noise calculators. The output of a self-interference noise calculator may be used to compensate for the interference experienced due to signals transmitted by another antenna of the same wireless device or system. In implementing such a self-interference noise calculator, a selected wireless relaying device or wireless destination device may operate in a full-duplex mode, such that relayed messages may be transmitted as well as information from other sources or destinations during a common time period (e.g., symbol, slot, subframe, etc.).

公开(公告)号：US12176312B2

公开(公告)日：2024-12-24

申请号：US18402426

申请日：2024-01-02

Applicant: Micron Technology, Inc.

Inventor： Chao Wen Wang

IPC: H01L21/00 ,  H01L23/00

Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.

公开(公告)号：US12176300B2

公开(公告)日：2024-12-24

申请号：US18209231

申请日：2023-06-13

Applicant: Micron Technology, Inc.

Inventor： Andrew Zhe Wei Ong ,  Liu Ziyan ,  Soo Ting Helen Yee ,  Qitao Fu

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B43/27

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers of respective memory cells and control gates, the tier located one over another over a substrate, the control gates including a control gate closest to the substrate, the control gates including respective portions forming a staircase structure; conductive contacts contacting the control gates at a location of the staircase structure, the conductive contacts including a conductive contact contacting the control gate; a dielectric structure located on sidewalls of the control gates; and support structures adjacent the conductive contacts and having lengths extending vertically from the substrate, the support structures including a support structure closest to the conductive contact, the support structure located at a distance from an edge of the dielectric structure, wherein a ratio of a width of the support structure over the distance is ranging from 1.6 to 2.0.

公开(公告)号：US12176034B2

公开(公告)日：2024-12-24

申请号：US17583472

申请日：2022-01-25

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  M. Jared Barclay ,  John D. Hopkins

IPC: H01L29/76 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually extend through a lowest of the conductive tiers. Insulative rings are in the lowest conductive tier in the TAV region. Individual of the insulative rings encircle individual of the TAVs. The insulative rings extend through the lowest conductive tier and into the conductor tier. Outer rings are in the lowest conductive tier that individually encircle one of the individual insulative rings that encircle the individual TAVs. Other embodiments, including method, are disclosed.