公开(公告)号：US12165962B2

公开(公告)日：2024-12-10

申请号：US17121093

申请日：2020-12-14

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Mohammad Enamul Kabir ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L23/48

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components coupled by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include a first microelectronic component including a first guard ring extending through at least a portion of a thickness of and along a perimeter; a second microelectronic component including a second guard ring extending through at least a portion of a thickness of and along a perimeter, where the first and second microelectronic components are coupled by direct bonding; and a seal ring formed by coupling the first guard ring to the second guard ring. In some embodiments, a microelectronic assembly may include a microelectronic component coupled to an interposer that includes a first liner material at a first surface; a second liner material at an opposing second surface; and a perimeter wall through the interposer and connected to the first and second liner materials.

公开(公告)号：US12165720B2

公开(公告)日：2024-12-10

申请号：US17033043

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Corey Gough ,  Nityasrilalitha Gollamudi ,  Mihir Patel

IPC: G11C16/34 ,  G06F11/07 ,  G06F11/14

Abstract: Systems, apparatuses and methods may provide technology for intelligent drive wear management. The technology may include determining a difference between a wear value derived for a first solid state storage drive and a wear value derived for a second solid state storage drive, and if the difference in wear value exceeds a wear skew threshold, swapping content between the first drive and the second drive. The technology may also include sorting an array of solid state storage drives into a plurality of drive groups based on a wear value derived for each drive, and determining, for a first pair of drives in a drive group, a difference in wear value between the drives in the first pair. Respective pairs of drives in a drive group may be selected based on the drive wear value and a drive rotation counter value associated with each drive. The technology may further include determining an average wear value for each drive group based on the wear values of each drive in the drive group and providing for maintenance service for the drives in the drive group if the average wear value for the drive group exceeds a potential drive failure threshold.

公开(公告)号：US12164977B2

公开(公告)日：2024-12-10

申请号：US17133112

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Patrick G. Kutch ,  Alexander Bachmutsky ,  Nicolae Octavian Popovici

IPC: G06F9/54 ,  G06F11/30 ,  G06F11/34 ,  G06F12/06 ,  G06F30/392 ,  G06Q10/101 ,  H04L41/50

Abstract: An apparatus comprising a network interface controller comprising a queue for messages for a thread executing on a host computing system, wherein the queue is dedicated to the thread; and circuitry to send a notification to the host computing system to resume execution of the thread when a monitoring rule for the queue has been triggered.

公开(公告)号：US12164695B2

公开(公告)日：2024-12-10

申请号：US17825872

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Manan Goel ,  Saurin Shah ,  Lakshman Krishnamurthy ,  Steven Xing ,  Matthew Pinner ,  Kevin James Doucette

IPC: G06F3/01 ,  G06F3/03 ,  G06F3/042 ,  G06F3/16 ,  G06V40/20 ,  G10H1/00

Abstract: Gesture-controlled virtual reality systems and methods of controlling the same are disclosed herein. An example apparatus includes an on-body sensor to output first signals associated with at least one of movement of a body part of a user or a position of the body part relative to a virtual object and an off-body sensor to output second signals associated with at least one of the movement or the position relative to the virtual object. The apparatus also includes at least one processor to generate gesture data based on at least one of the first or second signals, generate position data based on at least one of the first or second signals, determine an intended action of the user relative to the virtual object based on the position data and the gesture data, and generate an output of the virtual object in response to the intended action.

公开(公告)号：US12164462B2

公开(公告)日：2024-12-10

申请号：US17132663

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Ilya K. Ganusov ,  Ashish Gupta ,  Chee Hak Teh ,  Sean R. Atsatt ,  Scott Jeremy Weber ,  Parivallal Kannan ,  Aman Gupta ,  Gary Brian Wallichs

IPC: G06F15/78 ,  H04L45/60 ,  H04L49/109

Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.

公开(公告)号：US12164457B2

公开(公告)日：2024-12-10

申请号：US17899582

申请日：2022-08-30

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: G06F13/42 ,  G06F13/40

Abstract: Aspects of the embodiments are directed to a port comprising hardware to support the multi-lane link, the link comprising a lane that comprises a first differential signal pair and a second differential signal pair. Link configuration logic, implemented at least in part in hardware circuitry, can determine that the port comprises hardware to support one or both of receiving data on the first differential signal pair or transmitting data on the second differential signal pair, and reconfigure the first differential signal pair to receive data with the second differential signal pair or reconfigure the second differential signal pair to transmit data with the first differential signal pair; and wherein the port is to transmit data or receive data based on reconfiguration of one or both the first differential signal pair and the second differential signal pair.

公开(公告)号：US12164444B2

公开(公告)日：2024-12-10

申请号：US17357829

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Rajesh Sankaran ,  Rupin Vakharwala ,  Utkarsh Y. Kakaiya

IPC: G06F13/16 ,  G06F13/42 ,  G06F9/455

Abstract: Techniques and mechanisms for an input-output memory management module (IOMMU) to indicate to software whether a page request by an endpoint device is to be serviced. In an embodiment, the IOMMU receives from the endpoint device a response to an invalidation wait message. Based on the response, the IOMMU provides first information which indicates to software that page requests have been flushed from the endpoint device. Page request message from the endpoint device are compatible with an interface standard which also comprises a stop marker message type. The first information is provided independent of the endpoint device providing any message which is of the stop marker message type. In another embodiment, the first information includes a drain marker generated by the IOMMU, or a snapshot of an address corresponding to an end of a page request queue.

公开(公告)号：US12164430B2

公开(公告)日：2024-12-10

申请号：US18470553

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Vasileios Porpodas ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Wei-Yu Chen

IPC: G06F12/0862 ,  G06F8/41 ,  G06F9/30 ,  G06F12/0875

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more EUs.

公开(公告)号：US12164373B2

公开(公告)日：2024-12-10

申请号：US17339754

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： Bill Nale ,  Kuljit S. Bains ,  Lawrence Blankenbeckler ,  Ronald Anderson ,  Jongwon Lee

IPC: G06F11/00 ,  G06F11/10 ,  G11C11/406 ,  G11C11/4096

Abstract: A memory chip is described. The memory chip includes storage cells along a row of the memory chip's storage cell array to store a count value of the row's activations and error correction code (ECC) information to protect the count value. The memory chip includes ECC read logic circuitry to correct an error in the count value. The memory chip includes a comparator to compare the count value against a threshold. The memory chip includes circuitry to increment the count value if the count value is deemed not to have reached the threshold and ECC write logic circuitry to determine new ECC information for the incremented count value, and write driver circuitry to write the incremented count value and the new ECC information into the storage cells. The memory chip includes circuitry to cause the row to be refreshed if the count value is deemed to have reached the threshold.

公开(公告)号：US12164367B2

公开(公告)日：2024-12-10

申请号：US17126148

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Rafael Rosales ,  Michael Paulitsch ,  David Israel González Aguirre ,  Florian Geissler ,  Ralf Graefe

IPC: G06F11/00 ,  G06F11/07 ,  G06F16/901 ,  G06N7/01

Abstract: A computer-implemented method may include obtaining, from a system using a middleware component of the system, run-time evidence of the system; applying the obtained run-time evidence to a Directed Acyclic Graph (DAG) Bayesian network to determine marginal probabilities for one or more nodes of the DAG Bayesian network, wherein the DAG Bayesian network comprises a plurality of nodes each representing states and faults of the system, wherein each node includes a parameterized conditional probability distribution, and wherein one or more of the nodes of the plurality of nodes specify a list of one or more safety goals and a safety value; determining which nodes representing faults have probabilities exceeding their specified safety value; and determining one or more risk mitigation techniques to activate for the determined nodes representing faults with probabilities exceeding their respective safety value.