公开(公告)号：US12165695B2

公开(公告)日：2024-12-10

申请号：US17737999

申请日：2022-05-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sang-Kyun Park ,  Yuan He ,  Hiroshi Akamatsu

IPC: G11C7/00 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091

Abstract: Apparatuses including a level shifter circuit are disclosed. An example apparatus according to the disclosure includes a plurality of array access control circuits and a level shifter circuit. The plurality of array access control circuits receive an access control signal and a respective plurality of section enable signals. An array access control circuit of the plurality of array access control circuits provides a section access control signal responsive to the access control signal when a respective section enable signal is in an active state. The level shifter circuit receives a control signal and provides an access control signal responsive to the first signal. A first logic level of the control signal is represented by a first power supply voltage and a first logic level of the access control signal is represented by a second power supply voltage greater than the first power supply voltage.

公开(公告)号：US12164810B2

公开(公告)日：2024-12-10

申请号：US18216115

申请日：2023-06-29

Applicant: Micron Technology, Inc.

Inventor： Chandra M. Guda

IPC: G06F3/06 ,  G06F11/36

Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising receiving a memory access command; responsive to detecting that the memory access command satisfies a trigger condition, recording, in a set of registers, data associated with a plurality of events performed by processing the memory access command; and responsive to detecting that the set of registers comprises the data, disabling write operations on the set of registers.

公开(公告)号：US12164803B2

公开(公告)日：2024-12-10

申请号：US17327530

申请日：2021-05-21

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G06F3/06 ,  G06F13/16

Abstract: Memory devices and systems with memory-initiated command insertion (and associated methods) are disclosed herein. In one embodiment, a memory device comprises a command insertion terminal configured to be operably connected to a memory controller. The memory device can (i) identify a condition that can be addressed by receiving a command from the memory controller, and (ii) output, via the command insertion terminal, the command or an indication of the condition such that the command is inserted into a command queue of the memory controller. The memory device can include a command terminal over which the memory device can receive the command from the memory controller after the command is inserted in the command queue. In some embodiments, the condition can be a memory region of the memory device requiring a refresh cycle, and the command can be a command to perform a refresh cycle on the memory region.

公开(公告)号：US12164795B2

公开(公告)日：2024-12-10

申请号：US18390844

申请日：2023-12-20

Applicant: Micron Technology, Inc.

Inventor： Sourabh Dhir ,  Kang-Yong Kim

IPC: G06F12/00 ,  G06F3/06

Abstract: Methods, systems, and devices for improved inter-memory movement in a multi-memory system are described. A memory device may receive from a host device a command to move data from a first memory controlled by a first controller to a second memory controller by a second controller. The memory device may use the first and second controllers to facilitate the movement of the data from the first memory to the second memory via a path external to the host device. The memory device may indicate to the host device when to suspend activity to the first memory or the second memory and when to resume activity to the first memory or second memory.

公开(公告)号：US12164786B2

公开(公告)日：2024-12-10

申请号：US17420173

申请日：2021-04-28

Applicant: Micron Technology, Inc.

Inventor： Liang Ge

IPC: G06F3/00 ,  G06F1/324 ,  G06F3/06

Abstract: Methods, systems, and devices for a light hibernation mode for memory are described. A memory system may include volatile memory and non-volatile memory and may be configured to operate according to a first mode of operation (e.g., associated with relatively high power consumption), a light hibernation mode (e.g., a second mode associated with decreased power consumption in comparison to the first mode), and a full hibernation mode (e.g., a third mode of operation associated with decreased power consumption in comparison to the light hibernation mode). While operating according to the light hibernation mode, the memory system may maintain a greater quantity of data in the volatile memory relative to the full hibernation mode, which may avoid at least some power consumption related to data transfers between the volatile memory and non-volatile memory that may occur in connection with entering and exiting the full hibernation mode.

公开(公告)号：US12164769B2

公开(公告)日：2024-12-10

申请号：US17739755

申请日：2022-05-09

Applicant: Micron Technology, Inc.

Inventor： Zhenming Zhou ,  Ying Yu Tai

IPC: G06F3/06 ,  G06F11/30

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide adaptive media management based on memory component reliabilities. The controller can access configuration data to determine a reliability grade associated with individual groups of the memory components. The controller can then adaptively select between different media management operations based on the reliability grade associated with each individual group of the memory components.

公开(公告)号：US12164464B2

公开(公告)日：2024-12-10

申请号：US18386880

申请日：2023-11-03

Applicant: Micron Technology, Inc.

Inventor： Tony M. Brewer

IPC: G06F15/82 ,  G06F9/30 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0875 ,  G06F13/40

Abstract: Representative apparatus, method, and system embodiments are disclosed for a self-scheduling processor which also provides additional functionality. Representative embodiments include a self-scheduling processor, comprising: a processor core adapted to execute a received instruction; and a core control circuit adapted to automatically schedule an instruction for execution by the processor core in response to a received work descriptor data packet. In another embodiment, the core control circuit is also adapted to schedule a fiber create instruction for execution by the processor core, to reserve a predetermined amount of memory space in a thread control memory to store return arguments, and to generate one or more work descriptor data packets to another processor or hybrid threading fabric circuit for execution of a corresponding plurality of execution threads. Event processing, data path management, system calls, memory requests, and other new instructions are also disclosed.

公开(公告)号：US20240407080A1

公开(公告)日：2024-12-05

申请号：US18652581

申请日：2024-05-01

Applicant: Micron Technology, Inc.

Inventor： Quang Nguyen ,  Koustav Sinha ,  Christopher Glancey

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/00

Abstract: Systems, apparatuses, and methods related to a printed circuit board (PCB) with a plurality of layers are described. Embodiments of the present technology can include low coefficient of thermal expansion (CTE) strips, such as material with a CTE value of less than a threshold level, added into the core layer of the PCB. The added low CTE strips can lower the overall CTE mismatch between the PCB and the mounted components.

公开(公告)号：US20240404606A1

公开(公告)日：2024-12-05

申请号：US18803290

申请日：2024-08-13

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Fabio Pellizzer ,  Nevil N. Gajera

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: Systems, methods and apparatus to determine a programming mode of a set of memory cells that store an indicator of the programming mode. In response to a command to read the memory cells in a memory device, a first read voltage is applied to the memory cells to identify a first subset of the memory cells that become conductive under the first read voltage. The determination of the first subset is configured as an operation common to different programming modes. Based on whether the first subset of the memory cell includes one or more predefined memory cells, the memory device determines a programming mode of memory cells. Once the programming mode is identified from the common operation, the memory device can further execute the command to determine a data item stored, via the programming mode, in the memory cells.

公开(公告)号：US20240403205A1

公开(公告)日：2024-12-05

申请号：US18615046

申请日：2024-03-25

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/02

Abstract: Devices and methods are disclosed, including receiving, by a memory controller of a memory device, a memory request from a host device; collecting packet trace data from the memory request; including the packet trace data in a log stored in a memory array of the memory device; and returning the log to the host device.