公开(公告)号：US20220367694A1

公开(公告)日：2022-11-17

申请号：US17330420

申请日：2021-05-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Chun-Liang Hou ,  Wen-Jung Liao ,  Ruey-Chyr Lee

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/45 ,  H01L29/40

Abstract: A semiconductor transistor structure with reduced contact resistance includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a two-dimensional electron gas (2DEG) layer at an interface between the barrier layer and the channel layer, and a recess in a contact region. The recess penetrates through the barrier layer and extends into the channel layer. An Ohmic contact metal is disposed in the recess. The Ohmic contact metal is in direct contact with a vertical side surface of the barrier layer in the recess and in direct contact with an inclined side surface of the 2DEG layer and the channel layer in the recess.

公开(公告)号：US20220367693A1

公开(公告)日：2022-11-17

申请号：US17396793

申请日：2021-08-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Po-Wen Su ,  Chih-Tung Yeh

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L21/311

Abstract: A semiconductor structure includes a substrate, a stacked structure on the substrate, an insulating layer on the stacked structure, a passivation layer on the insulating layer, and a contact structure through the passivation layer and the insulating layer and directly contacting the stacked structure. The insulating layer has an extending portion protruding from a sidewall of the passivation layer and adjacent to a surface of the stacked structure directly contacting the contact structure.

公开(公告)号：US20220365444A1

公开(公告)日：2022-11-17

申请号：US17348806

申请日：2021-06-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Guo-Xin HU ,  Yuh-Kwei CHAO ,  Chung-Yi CHIU

IPC: G03F7/20 ,  G06T7/00 ,  G06K9/46 ,  G06K9/62 ,  G06N20/00

Abstract: An optical proximity correction (OPC) operation method and an OPC operation device are provided. The OPC operation method includes the following steps. A mask layout is obtained. If the mask layout contains at least one defect hotspot, at least one partial area pattern is extracted from the mask layout according to the at least defect hotspot. A machine learning model is used to analyze the local area pattern to obtain at least one OPC strategy. The OPC strategy is implemented to correct the mask layout.

公开(公告)号：US20220365433A1

公开(公告)日：2022-11-17

申请号：US17316736

申请日：2021-05-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Hsuan Chang ,  Da-Jun Lin ,  Yao-Hsien Chung ,  Ting-An Chien ,  Bin-Siang Tsai ,  Chih-Wei Chang ,  Shih-Wei Su ,  Hsu Ting ,  Sung-Yuan Tsai

IPC: G03F7/075 ,  G03F7/20

Abstract: A fabricating method of reducing photoresist footing includes providing a silicon nitride layer. Later, a fluorination process is performed to graft fluoride ions onto a top surface of the silicon nitride layer. After the fluorination process, a photoresist is formed to contact the top surface of the silicon nitride layer. Finally, the photoresist is patterned to remove at least part of the photoresist contacting the silicon nitride layer.

公开(公告)号：US20220359740A1

公开(公告)日：2022-11-10

申请号：US17335049

申请日：2021-05-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsiao Chen ,  Kai-Lin Lee ,  Wei-Jen Chen

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: A high electron mobility transistor includes a substrate. A channel layer is disposed on the substrate. An active layer is disposed on the channel layer. The active layer includes a P-type aluminum gallium nitride layer. A P-type gallium nitride gate is disposed on the active layer. A source electrode and a drain electrode are disposed on the active layer.

公开(公告)号：US20220359582A1

公开(公告)日：2022-11-10

申请号：US17333040

申请日：2021-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yu Hsieh

IPC: H01L27/146

Abstract: An image sensor includes a semiconductor substrate, a first isolation structure, a visible light detection structure, and an infrared light detection structure. The semiconductor substrate has a first surface and a second surface opposite to the first surface in a vertical direction. The first isolation structure is disposed in the semiconductor substrate for defining pixel regions in the semiconductor substrate. The visible light detection structure and the infrared light detection structure are disposed within the same pixel region, and a first portion of the visible light detection structure is disposed between the second surface of the semiconductor substrate and the infrared light detection structure in the vertical direction.

公开(公告)号：US11495686B2

公开(公告)日：2022-11-08

申请号：US17147468

申请日：2021-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Tang ,  Chung-Ting Huang ,  Bo-Shiun Chen ,  Chun-Jen Chen ,  Yu-Shu Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first spacer adjacent to the gate structure, forming a second spacer adjacent to the first spacer, forming an epitaxial layer adjacent to the second spacer, forming a second cap layer on the epitaxial layer, and then forming a first cap layer on the second cap layer. Preferably, a top surface of the first cap layer includes a V-shape and the first cap layer and the second cap layer are made of different materials.

公开(公告)号：US11495681B2

公开(公告)日：2022-11-08

申请号：US17067775

申请日：2020-10-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Ching-Chung Yang ,  Shan-Shi Huang ,  Shin-Hung Li ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chiu-Te Lee ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chia-Jung Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28

Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.

公开(公告)号：US20220352459A1

公开(公告)日：2022-11-03

申请号：US17867702

申请日：2022-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  H01F41/34 ,  H01F10/32 ,  G11C11/16

Abstract: A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.

公开(公告)号：US20220352195A1

公开(公告)日：2022-11-03

申请号：US17864435

申请日：2022-07-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  ZHIGUO LI ,  CHI REN

IPC: H01L27/11578 ,  H01L29/66 ,  H01L27/11551 ,  H01L29/78

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for FinFET includes a fin, a control gate and a selective metal gate. The fin is on a top surface of a substrate, wherein the fin has two sidewalls and a top surface, and the fin includes a memory region and a logic region. The control gate is disposed over the fin of the memory region and covers the two sidewalls and the top surface of the fin, wherein the control gate includes a charge trapping layer and a control electrode, wherein the charge trapping layer is sandwiched by the fin and the control electrode. The selective metal gate is disposed over the fin adjacent to the control gate and covers the two sidewalls and the top surface of the fin. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.