公开(公告)号：US20040121498A1

公开(公告)日：2004-06-24

申请号：US10657801

申请日：2003-09-08

Applicant: STMicroelectronics S.r.I.

Inventor： Camillo Bresolin ,  Valter Soncini ,  Andrea Riva

IPC: H01L021/66 ,  H01L021/336 ,  H01L021/04

CPC classification number: H01J37/3171 ,  H01J37/18 ,  H01J2237/022

Abstract: An ion-implantation machine has an implantation chamber with a vent inlet; a vacuum pump is connected to the implantation chamber through a vacuum valve. A pipe connects the vent inlet of the implantation chamber to a source of a fluid containing oxygen. The fluid containing oxygen is preferably environmental air. A flow-rate control valve is arranged on the pipe and is activated only after closing the vacuum valve.

Abstract translation: 离子注入机具有具有通气口的注入室; 真空泵通过真空阀与注入室连接。 管将注入室的排气入口连接到含有氧气的流体源。 含氧的流体优选是环境空气。 流量控制阀配置在管道上，仅在关闭真空阀后启动。

公开(公告)号：US20040070888A1

公开(公告)日：2004-04-15

申请号：US10601332

申请日：2003-06-20

Applicant: STMicroelectronics S.r.I.

Inventor： Ubaldo Mastromatteo ,  Bruno Murari ,  Paolo Ferrari ,  Simone Sassolini

IPC: G11B005/56

CPC classification number: B81B3/0021 ,  H02N1/006

Abstract: A micro-electro-mechanical device formed by a body of semiconductor material having a thickness and defining a mobile part and a fixed part. The mobile part is formed by a mobile platform, supporting arms extending from the mobile platform to the fixed part, and by mobile electrodes fixed to the mobile platform. The fixed part has fixed electrodes facing the mobile electrodes, a first biasing region fixed to the fixed electrodes, a second biasing region fixed to the supporting arms, and an insulation region of insulating material extending through the entire thickness of the body. The insulation region insulates electrically at least one between the first and the second biasing regions from the rest of the fixed part.

Abstract translation: 由具有厚度并限定可移动部分和固定部分的半导体材料体形成的微电子机械装置。 可移动部分由移动平台，从移动平台延伸到固定部分的支撑臂，以及固定到移动平台的移动电极形成。 固定部分具有面向移动电极的固定电极，固定到固定电极的第一偏置区域，固定到支撑臂的第二偏压区域以及延伸穿过主体整个厚度的绝缘材料的绝缘区域。 绝缘区域在第一和第二偏压区域之间至少一个与固定部件的其余部分绝缘。

公开(公告)号：US20040059894A1

公开(公告)日：2004-03-25

申请号：US10612825

申请日：2003-07-01

Applicant: STMicroelectronics S.r.I.

Inventor： Fabrizio Simone Rovati ,  Antonio Maria Borneo ,  Danilo Pietro Pau

IPC: G06F015/00 ,  G06F015/76

CPC classification number: G06F9/3879 ,  G06F9/3853 ,  G06F9/3877

Abstract: The program to be executed is compiled by translating it into native instructions of the instruction-set architecture of the processor system, organizing the instructions deriving from the translation of the program into respective bundles in an order of successive bundles, each bundle grouping together instructions adapted to be executed in parallel by the processor system. The bundles of instructions are ordered into respective sub-bundles, said sub-bundles identifying a first set of instructions, which must be executed before the instructions belonging to the next bundle of said order, and a second set of instructions, which can be executed both before and in parallel with respect to the instructions belonging to said subsequent bundle of said order. There is defined a sequence of execution of the instructions in successive operating cycles of the processor system, assigning each sub-bundle to an operating cycle, thus preventing simultaneous assignment to the same operating cycle of two sub-bundles belonging to the first set of two successive bundles. The instructions of the sequence may be executed by the various processors of the system in conditions of binary compatibility.

Abstract translation: 将要执行的程序通过将其转换为处理器系统的指令集体系结构的本机指令而进行编译，将按程序的翻译导出的指令按照连续的捆的顺序进行组织， 由处理器系统并行执行。 所述指令束被排列到相应的子束中，所述子束标识第一组指令，其必须在属于所述命令的下一束的指令之前执行，以及可以执行的第二组指令 在属于所述顺序的所述后续束的指令之前和之后。 在处理器系统的连续操作周期中定义了执行指令的顺序，将每个子束分配到操作周期，从而防止同时分配属于第一组二的两个子束的相同操作周期 连续捆绑 序列的指令可以由系统的各种处理器在二进制兼容性的条件下执行。

公开(公告)号：US20040058493A1

公开(公告)日：2004-03-25

申请号：US10621262

申请日：2003-07-15

Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics S.A.

Inventor： Nicolas Demange ,  Raffaele Zambrano

IPC: H01L021/8234 ,  H01L021/8244 ,  H01L021/8242

CPC classification number: H01L27/11502 ,  H01L27/10811 ,  H01L27/10888 ,  H01L27/115 ,  H01L27/11507

Abstract: The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material and the same plate line. In this way, the manufacturing process is not critical and the size of the cells is minimal.

Abstract translation: 层叠型电池单元包括形成在半导体材料的衬底的有源区和形成在有源区上方的电容器的MOS晶体管; 每个MOS晶体管具有第一和第二导电区域和控制电极，并且每个电容器具有由电介质区域材料（例如铁电体）隔开的第一和第二板。 每个MOS晶体管的第一导电区域连接到相应电容器的第一板，每个MOS晶体管的第二导电区域连接到相应的位线，每个MOS晶体管的控制电极连接到相应的字线， 每个电容器的第二板连接到相应的板线。 平板线垂直于位线延伸并平行于字线。 在与位线的平行方向上相邻的至少两个单元共享相同的介电区材料和相同的板线。 以这种方式，制造过程不是关键的，并且电池的尺寸是最小的。

公开(公告)号：US20040044923A1

公开(公告)日：2004-03-04

申请号：US10229377

申请日：2002-08-27

Applicant: STMicroelectronics S.r.I

Inventor： Alberto Battaia

IPC: G06F001/04

CPC classification number: G06F1/14

Abstract: The timing system includes a plurality of timing units interconnected to perform a count operation. Software programmable registers interconnect the plurality of timing units, and a control circuit generates a clock signal for the plurality of timing units. The control circuit includes an interface for connection to an external bus to receive and transmit data.

Abstract translation: 定时系统包括互连以执行计数操作的多个定时单元。 软件可编程寄存器互连多个定时单元，并且控制电路产生用于多个定时单元的时钟信号。 控制电路包括用于连接到外部总线以接收和发送数据的接口。

公开(公告)号：US20040036999A1

公开(公告)日：2004-02-26

申请号：US10464435

申请日：2003-06-16

Applicant: STMicroelectronics S.r.I.

Inventor： Francesco Chrappan Soldavini ,  Roberto Oboe ,  Paolo Capretta

IPC: G11B005/596 ,  G11B021/02

CPC classification number: H02P25/034

Abstract: A method of driving an electrical load having a complex electrical impedance, such as a voice-coil motor controlling the position of a read/write head in a data storage disk drive system, comprises providing a voltage-mode driver generating drive signals for the electrical load in response to drive commands. Compensated commands for the voltage-mode driver are generated filtering the drive commands, compensating for a phase shift between electrical quantities delivered to the electrical load. The voltage-mode drive thus emulates a conventional, but more expensive, current-mode drive. In a preferred embodiment, the method comprises estimating characteristic parameters of the electrical load during the operation, and adapting the filtering to the estimated characteristic parameters. The estimation comprises implementing a Kalman filtering algorithm, particularly an extended Kalman filtering.

Abstract translation: 驱动具有复电阻抗的电负载的方法，例如控制数据存储盘驱动系统中读/写头位置的音圈电机，包括提供电压模式驱动器，产生用于电 响应驱动命令加载。 产生用于电压模式驱动器的补偿命令，对驱动命令进行滤波，补偿传送到电负载的电量之间的相移。 因此，电压模式驱动器模拟常规但是更昂贵的电流模式驱动器。 在优选实施例中，该方法包括估计操作期间的电负载的特征参数，以及使滤波适应估计的特征参数。 估计包括实现卡尔曼滤波算法，特别是扩展卡尔曼滤波。

公开(公告)号：US20040032403A1

公开(公告)日：2004-02-19

申请号：US10445137

申请日：2003-05-23

Applicant: STMicroelectronics S.r.I. and DORA S.p.A.

Inventor： Leonardo Sala ,  Daniele Domanin ,  Roberto Gariboldi

IPC: G09G005/00

CPC classification number: G09G3/3625 ,  G09G3/2018 ,  G09G3/2022 ,  G09G2320/0247 ,  G09G2320/0266

Abstract: The present invention relates to a driving method for flat panel display devices, particularly a driving method combining a Multi Line Addressing (MLA) technique and a Frame Rate Control (FRC) technique, for flat panel display devices such as Liquid Crystal Display (LCD). In an embodiment the method of driving an image display device comprises the following steps: dividing row electrodes of an image device, having a plurality of row electrodes and a plurality of column electrodes, into a plurality of subgroups; selecting one of the plurality of said subgroups having a prefixed number of electrodes; performing a gray scale display by a frame rate control (FRC) by using a prefixed number of frames and a prefixed number of bits representing the gray levels; decomposing one of said frame in a number of time instants proportional to said prefixed number of electrodes; putting the bits representing the gray levels equally distributed in said prefixed number of frames.

Abstract translation: 本发明涉及用于平板显示装置的驱动方法，特别是组合多线寻址（MLA）技术和帧速率控制（FRC）技术的驱动方法，用于诸如液晶显示器（LCD）的平板显示装置， 。 在一个实施例中，驱动图像显示装置的方法包括以下步骤：将具有多个行电极和多个列电极的图像装置的行电极分成多个子组; 选择所述多个所述子组中的一个具有预定数量的电极; 通过使用预定数量的帧和表示灰度级的前缀数目的比特来执行帧速率控制（FRC）的灰度级显示; 在与所述预定数量的电极成比例的多个时刻中分解所述帧中的一个; 将表示灰度级的位平均分配在所述前缀数目的帧中。

公开(公告)号：US20030235013A1

公开(公告)日：2003-12-25

申请号：US10429266

申请日：2003-05-02

Applicant: STMicroelectronics S.r.I.

Inventor： Marco Del Sarto ,  Mauro Marchi ,  Lorenzo Baldo ,  Simone Sassolini

IPC: G11B005/56

CPC classification number: G11B5/4826

Abstract: A read/write assembly for magnetic hard disks includes at least: one supporting element; one read/write (R/W) transducer; one micro-actuator, set between the R/W transducer and the supporting element; one electrical-connection structure for connection to a remote device carried by the supporting element and connected to the R/W transducer and to the micro-actuator. In addition, a protective structure, set so as to cover the micro-actuator is made of a single piece with the electrical-connection structure.

Abstract translation: 用于磁性硬盘的读/写组件至少包括：一个支撑元件; 一个读/写（R / W）传感器; 一个微致动器，设置在R / W换能器和支撑元件之间; 一个电连接结构，用于连接到由支撑元件承载并连接到R / W传感器和微致动器的远程设备。 此外，设置成覆盖微致动器的保护结构由具有电连接结构的单件制成。

公开(公告)号：US20030201503A1

公开(公告)日：2003-10-30

申请号：US10430771

申请日：2003-05-06

Applicant: STMicroelectronics, S.r.I.

Inventor： Ferruccio Frisina

IPC: H01L029/76

CPC classification number: H01L29/7802 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/66712

Abstract: MOS-gated power device including a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type. A plurality of doped regions of a first conductivity type is formed in the semiconductor material layer, each one of the doped regions being disposed under a respective body region and being separated from other doped regions by portions of the semiconductor material layer.

Abstract translation: 包括多个基本功能单元的MOS门控功率器件，每个基本功能单元包括形成在第二导电类型的半导体材料层中的第一导电类型的体区。 在半导体材料层中形成第一导电类型的多个掺杂区域，每个掺杂区域设置在相应的主体区域下方，并且通过半导体材料层的一部分与其它掺杂区域分离。

公开(公告)号：US20030182533A1

公开(公告)日：2003-09-25

申请号：US10371221

申请日：2003-02-21

Applicant: STMicroelectronics S.r.I.

Inventor： Salvatore Poli ,  Paolino Schillaci ,  Salvatore Polizzi

IPC: G06F012/00 ,  G06F012/14

CPC classification number: G11C16/22

Abstract: The invention provides a protocol cycle during which a memory address and all the data bytes to be written are transmitted, and the writing process is carried out only once for all the transmitted data bytes, by writing a first byte in the memory sector corresponding to a first address generated by resetting to zero the 2 least significant bits of the transmitted address and all the other transmitted bytes in successive addresses. The method includes writing a certain number N of data bytes, in consecutive memory addresses in a memory array of a memory device, and includes unprotecting the memory sectors in which data are to be written, communicating the programming command to the memory device, communicating to the memory device the bits to be stored and specifying a relative memory address of a sector to write in, and writing the data bits in the memory.

Abstract translation: 本发明提供了一种协议周期，在该协议周期期间，发送存储器地址和要写入的所有数据字节，并且通过在对应于一个存储器区域的存储器扇区中写入第一个字节，对所有发送的数据字节仅执行一次写入处理 通过将所发送的地址的2个最低有效位和连续地址中的所有其他发送字节重置为零而产生的第一地址。 该方法包括在存储器件的存储器阵列中的连续存储器地址中写入一定数量的N个数据字节，并且包括不保护要写入数据的存储器扇区，将编程命令传送到存储器件，与 存储器件将要存储的位并指定要写入的扇区的相对存储器地址，以及将数据位写入存储器。